Abstract: A method for overlap-adding signals useful for performing frame loss concealment (FLC) in an audio decoder as well as in other applications. The method uses a dynamic mix of windows to overlap two signals whose normalized cross-correlation may vary from zero to one. If the overlapping signals are decomposed into a correlated component and an uncorrelated component, they are overlap-added separately using the appropriate window, and then added together. If the overlapping signals are not decomposed, a weighted mix of windows is used. The mix is determined by a measure estimating the amount of cross-correlation between overlapping signals, or the relative amount of correlated to uncorrelated signals.

Abstract: A method and system for refining an estimated pitch period estimate based on a coarse pitch useful for performing frame loss concealment in an audio decoder as well as for other applications. A normalized correlation at the coarse pitch lag is computed and used as the current best candidate. The normalized correlation is then evaluated at the midpoint of the refinement pitch range on either side of the current best candidate. If the normalized correlation at either midpoint is greater than the current best lag, the midpoint with the maximum correlation is selected as the current best lag. After each iteration, the refinement range is decreased by a factor of two and centered on the current best lag. This bisectional search continues until the pitch has been refined to an acceptable tolerance or until the refinement range has been exhausted. During each step of the bisectional pitch refinement, the signal is decimated to reduce the complexity of computing the normalized correlation.

Abstract: The present invention is directed to methods and systems for scaling receive protocol processing by allowing the network load from a network adapter to be balanced across multiple CPUs based on RSS and/or QoS traffic classification techniques.

Abstract: A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer.

Abstract: Data error often occurs during the process of data transmission or storage. Typically, a store-and-forward data switch uses the frame check sequence portion of a data frame to detect for error that occurred during transit to the switch. However, error could be introduced into the data frame when it is in the memory of the data switch. A network switch capable of single-error correction and double-error detection is provided to further protect the data frame while it is in the switch.

Abstract: A method is provided for payload header suppression within a wireless network in which a limited number of suppression indices are used to map suppression rules to data streams. Network resources are conserved by implementing precise classification algorithms to correctly identify incoming packets at the wireless device as belonging to a particular data stream, which ensures that a minimum number of suppression indices are utilized. Additionally, network resources are conserved by utilizing sophisticated algorithms for reusing suppression indices when new data streams are detected by the wireless device. One such reuse algorithm involves recycling the suppression index that has been least recently used in transmitting a packet with a suppressed payload header.

Abstract: An integrated circuit layout on a semiconductor substrate includes a plurality of circuit modules and power rails. One of the power rails is a positive voltage supply rail, and another one is a negative voltage supply rail or a ground rail. The positive voltage supply rail is located on a first layer of the semiconductor substrate. The negative voltage supply rail is located on a second layer of the semiconductor substrate. The second layer is located below the first layer. In this way, the integrated circuit layout area is reduced as negative voltage supply rail is moved to another layer.

Abstract: A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit board formed by a plurality of substantially partially overlapping bores. An electrically conductive plating is formed on an inner surface of the opening. The plating forms a plurality of distinct electrically conductive paths.

Abstract: A method of making a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the source regions to one of the first or second interconnect layers. A second plurality of contacts connect the drain regions to the other of the first or second interconnect layers. The first and second interconnect layers cover a region above the substrate area in which the plurality of transistors reside so as to achieve a low ohmic result. The second interconnect layer has openings therein for one of the respective first or second plurality of contacts to pass therethrough and couple to the at least one first interconnect layer. Either the first or second interconnect layers can function as an input or output for the circuit.

Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Abstract: A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality of data lines of the bus. Vertical line information is detected for the plurality of data lines to determine if there is a match with a training pattern. A skew distance is calculated once there is a match with the training pattern. Then, the plurality of data lines are bit aligned based on the skew distance.

Abstract: A carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system. In-phase signals are sampled twice a symbol at the in-phase symbol sampling time and at the quadrature-phase symbol sampling time. The signals are de-multiplexed to generate I and XI data streams, where I represents the in-phase sampling time signals and XI represents mid-symbol point sample times. A similar procedure is carrier out on quadrature-phase signals. When the in-phase signal is de-multiplexed to generate a symbol I, the quadrature-phase signal is de-multiplexed to generate its mid-symbol point XQ. Both I and Q are decoded to define a symbol error term, which is combined with the opposite mid-symbol signal to define a phase error term PI and PQ for each rail.

Abstract: Methods and systems for reducing interference in a signal are disclosed herein. Aspects of the method may comprise generating a first local oscillator signal. The generated first local oscillator signal may be phase-shifted to generate a second local oscillator signal and the second local oscillator signal may be phase-shifted to generate a third local oscillator signal. The first, second, and third local oscillator signals may be combined to generate a combined local oscillator signal, where a third harmonic and/or a fifth harmonic may be eliminated from the combined local oscillator signal. The generated second local oscillator signal may be multiplied by a factor of square root of two (?{square root over (2)}). The first and third local oscillator signals may be added to the multiplied second local oscillator signal. An input signal may be mixed with the generated combined local oscillator signal to generate a mixed output signal.

Abstract: The present invention relates a system and method for mitigating impairment in a communication system. In one embodiment, the system includes a transmitter adapted to transmit at least one signal and a receiver adapted to receive the at least one signal and mitigate inter code interference in the signal using at least one inter code interference coefficient.

Abstract: New version devices of a home phone line network may operate on a first carrier frequency (within the new version frequency band) while old version devices may operate at a second carrier frequency (within the old version frequency band). Preamble, header, and trailer portions of a new version signal include a plurality of spectral copies of a baseband modulated signal. One or more of these spectral copies of the baseband modulated signal is/are indistinguishable from corresponding components of an old version signal. The new version signal is transmit filtered to have a negatively sloping power spectral density in order to maintain a constant power level in relation to old version signals and to have slope that is opposite of binder crosstalk so as to form, with the average crosstalk, a constant level white noise floor.

Abstract: A differential amplifier is configured in a cascode configuration that includes input transistors that are connected to corresponding cascode transistors. The gates of the cascode transistors are tied together to form a common bias for the cascode devices. The input transistors of the differential amplifier receive a differential input signal that is amplified and outputted to an output circuit that is connected to the cascode transistors. The cascode devices require a bias voltage for proper operation. Preferably, the bias voltage puts the cascode devices into the saturation region. The gates of cascode devices are coupled together and connected to a bias terminal. In embodiments of the invention, the bias terminal is connected to another terminal of the chip to provide the bias for the cascode devices. This can include the input and output nodes if they have a well-defined and relatively fixed voltage.

Abstract: A small form factor USB Bluetooth dongle includes a printed circuit board (PCB), a USB contact area, and a radio frequency (RF) transceiver die. The PCB includes a first primary surface and a second primary surface. The USB contact area is fabricated on the first primary surface. The RF transceiver die is mounted on the second primary surface, wherein the RF transceiver is in accordance with Bluetooth.

Abstract: Systems and methods that identify the Upper Layer Protocol (ULP) message boundaries are provided. In one example, a method that identifies ULP message boundaries is provided. The method may include one or more of the following steps: attaching a framing header of a frame to a data payload to form a packet, the framing header being placed immediately after the byte stream transport protocol header, the framing header comprising a length field comprising a length of a framing protocol data unit (PDU); and inserting a marker in the packet, the marker pointing backwards to the framing header and being inserted at a preset interval.

Abstract: An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.

Abstract: Collecting traffic data regarding a plurality of wireless terminals includes periodically receiving Global Positioning System (GPS) location information from each of the plurality of wireless terminals by a location tracking server. For each of the plurality of wireless terminals, the location tracking server accumulates GPS location information. The location tracking server receives information regarding a geographic feature, processes the received GPS location information, and generates a traffic pattern report regarding the geographic feature based upon the accumulated GPS location information.