Abstract: An integrated circuit includes first, second and third circuits, a clock module and a rate adapting module. The first circuit causes frequency dependent noise and is clocked based on a clock signal. The second circuit is rate dependent and is clocked based on an operation dependent clock signal. The third circuit is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range. The clock module generates a clock signal having a rate such that frequency dependent noise components associated with the clock signal are outside the given frequency range. The rate adapting module is coupled to produce the operation dependent clock signal from the clock signal.

Abstract: Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-Well regions adjacent to one another without an isolation region in between.

Abstract: A communication device configured to assign a data packet to a memory bank of a memory device is provided. The communication device includes an input port for receiving the data packet, a look-ahead logic module, a pointer assignment module, and an output port. The look-ahead logic module is configured to select an address of the memory bank of the memory device by overriding an address mapping scheme that permits successive data packets to be assigned to the same memory bank. The pointer assignment module is configured to assign a pointer to the data packet based upon the memory bank determined by the look-ahead logic module. In addition, the output port is configured to transfer the data packet to the memory bank of the memory device.

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract: A network device for controlling data flow can have a buffer configured to receive a packet, a first determining unit configured to determine a multicast group number from the packet, a first table storage unit configured to store at least one first bit vector and at least one first pointer, and configured to have the multicast group number indexed thereto, and a second table storage unit configured to store at least one second bit vector and at least one second pointer, and configured to have the at least one first pointer indexed thereto.

Abstract: A system may adjust the times at which data is sampled by separate sampling mechanisms. Here, it may be desirable to ensure that one sampler samples data at substantially the same time as the other sampler. For example, output data from a high speed sampler that samples received data may be compared with an output of an analog to digital converter that samples the received data at a lower data rate. This difference or relative error may be accumulated over a period of time for given values of delay applied to the clock for the analog to digital converter. In this way, a delay value that minimizes the relative error may be selected as a desired delay value.

Abstract: A method and apparatus for controlling transmit power of a wireless communication device includes processing that begins when a transmitting wireless communication device transmits a packet to a targeted wireless device via a wireless channel of a communication system at a 1st power level. The processing continues by having the targeted wireless device determining signal strength of the packet received via the wireless channel. The processing then continues when the targeted and/or transmitting device determines the adequacy of the 1st power level based on the determined signal strength. If the 1st power level is adequate, the transmitting wireless device continues to transmit information at the 1st power level. If, however, the 1st power level is not adequate, the transmitting communication device adjusts its transmit power up or down to provide an adequate power level.

Abstract: One or more methods and/or systems of utilizing a memory external to an integrated circuit chip are presented. In one embodiment, the system comprises an integrated circuit containing a logic circuitry, a one time programmable memory, a control processor, and a data interface. In one embodiment, a method of storing data into a memory comprises programming one or more bits of a one time programmable memory, generating an identifier from the integrated circuit chip, and using the identifier to store data within the memory.

Abstract: A method for performing packet loss concealment (PLC) and/or frame erasure concealment (FEC) in a speech decoder of a voice communication system. In accordance with the method, if a segment of an encoded speech signal is determined to be bad, an excitation signal is derived by scaling a random sequence of samples, and long-term and short-term predictive parameters are derived based on parameters associated with a previously-decoded segment. The excitation signal is then filtered by a long-term synthesis filter and a short-term synthesis filter under the control of the respective long-term and short-term predictive parameters. If the number of consecutively-received bad segments exceeds a predetermined threshold, the decoded speech signal is gradually reduced.

Abstract: A frequency synthesizer for use in a transceiver generates a relatively high reference frequency with fine frequency resolution and low in-band phase noise by using a digital processor to generate a digital reference signal at a finely-tuned reference frequency. A Digital-to-Analog Converter (DAC) converts the digital reference signal to an analog reference signal, and a low pass filter filters the analog reference signal to produce a filtered analog reference signal. The frequency synthesizer further includes a phase locked loop for up-converting the filtered analog reference signal from an IF signal to an RF signal.

Abstract: Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for verifying a current performance of a command by a controller. A first cyclic redundancy check (CRC) for the command is prestored in memory. A second CRC for the command is calculated after instructions of the command have been performed by the controller. The first CRC is compared with the second CRC. Preferably, the controller is reset if the first CRC does not match the second CRC. Also, an address of a first instruction of the command is compared with an address of a second instruction of the command to determine if there may be a discontinuity between the first and the second instructions. It is determined if the first instruction is a valid instruction from/to which an instruction sequence of the command can be redirected.

Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

Abstract: In an RF communication system, aspects for supporting cellular or wireless network and broadcast utilizing an integrated single chip cellular and broadcast silicon solution may comprise receiving in a mobile terminal, a plurality of cellular frequency band communications services and VHF/UHF band broadcast services in a single baseband processor IC within a mobile terminal. Cellular information associated with the cellular frequency band communications service, and VHF/UHF broadcast information associated with the VHF/UHF broadcast service may be processed by a cellular processing module and a VHF/UHF broadcast processing module, respectively, integrated within a single integrated circuit within the mobile terminal. The cellular processing module and the VHF/UHF broadcast processing module within the mobile terminal may operate independently of each other to separately process the cellular information and the VHF/UHF broadcast information without exchanging related information.

Abstract: A method and apparatus for accessing, controlling and utilizing a network communication medium. Various aspects of the present invention may comprise a first networked device with power-save capability. The first networked device may acquire control of a communication medium utilizing a medium access protocol, which may be contention-based. The first networked device may utilize the communication medium to communicate information to a second networked device. The first networked device may transfer control of the communication medium to the second networked device, whereby the second networked device may control the communication medium without having to acquire control of the communication medium by utilizing the medium access protocol. The second networked device may utilize the communication medium to communicate information to the first networked device while maintaining control over the communication medium.

Abstract: A system and method for accelerated performance of quadrature amplitude modulation (QAM) is provided. The system includes multiple general purpose registers and multiple execution units configured to decode a set of QAM tones in parallel or an individual QAM tone in response to a single instruction executable by the processor. Each of the plurality of execution units is configured to decode one of the set of QAM tones according to a constellation size associated with the one of the set of QAM tones. The QAM decoding method includes reading a constellation size value for each of a set of received input tones. For each tone in the set of input tones, an ideal point in a QAM constellation of the associated constellation size closest to the X and Y coordinates of the tone is determined. The data values of the ideal points are then stored in a destination register.

Abstract: A video processing system captures a sequence of original video frames with a video camera, presents at least one frame of the sequence of original video frames on a video display, receives user input regarding the sequence of original video frames, and presents a sub-frame on the video display that corresponds to a region in at least one frame of the sequence of original video frames that is identified in the user input. The video processing system also generates metadata corresponding to the sub-frame, the metadata to be used by a target video player in modifying the sequence of original video frames to produce a full screen presentation on a target video display of the target video player corresponding to the sub-frame. Targeted sub-frame metadata can be specifically generated for use with a particular screen or screen size.

Abstract: In a digital communication infrastructure, intermediate network nodes compare packets from end-point devices with pluralities of virus templates. Upon detecting matches, virus service functions are invoked which interrupt the packet flow. Network wide template and service functionality updating is provided to service pluralities of virus service software vendors. Non-repetitive detection processing minimizes network load. Virus service functions may execute locally and/or remotely. Servicing may include dropping packets containing virus codes or, processing and routing the packets. Pop-up messages revealing underlying template matches are delivered with human challenge mechanism. The network nodes may be routers, packet switching exchanges, switches, access points, Internet service provider equipment, etc. External vendor servers and server clusters may assist network nodes in detecting and processing packets for virus codes.

Abstract: A system, method, and computer program product for synchronizing time between a centralized controller device and at least one subscriber device on a fiber access network. The control layer of a network device is expanded, and additional messaging control is added via the transmission of data frames. The expansion prevents reliance on a physical layer signal. The time synchronization also allows a time stamp to be incorporated into a message. Thus, bandwidth is not wasted by simply transmitting a time stamp by itself. In an embodiment, the centralized controller device measures the time difference between the time at which a particular ranging request is transmitted and the time at which the particular ranging request is received. The time difference represents the time adjustment value for the particular subscriber device and allows the device to synchronize its time with that of the centralized controller device.

Abstract: Wireless local area network (WLAN) management. A novel approach is provided to associate various wireless stations (STAs) to the WLAN via appropriately selected Access Point (APs). In one implementation, a first AP services only those STAs that have functionality of a first user class (e.g., 802.11b functionality in one instance). In addition, a second AP services only those STAs that have functionality of a second user class (e.g., 802.11g functionality). The WLAN management ensures that STAs having similar characteristics (or similar functionality) are grouped together and associated with an AP that corresponds to those characteristics. For example, 802.11b STAs associate with the WLAN via an 802.11b AP. Analogously, 802.11g STAs associate with the WLAN via an 802.11g AP. When an 802.11g STA is unable to associate with the WLAN via an 802.11g AP, the STA may shift down its functionality set to 802.11b to successfully associate with the WLAN.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.