Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.

Abstract: A video processing system applies sub-frame processing to video data to generate both a first sequence of sub-frames of video data and a second sequence of sub-frames of video data. The first sequence of sub-frames of video data and the second sequence of sub-frames of video data are defined by metadata. The processing circuitry generates a third sequence of sub-frames of video data by combining the first sequence of sub-frames of video data with the second sequence of sub-frames of video data. Adaptive video processing circuitry receives encoded source video data, raw source video data, similar display metadata, target display metadata, and/or target display information. The adaptive video processing circuitry processes its input information to produce one or more outputs that include tailored metadata, encoded target display video data, target display video data, and DRM/Billing Signaling.

Abstract: A cable modem system and method are provided for using a data compression dictionary to transmit compressed payload data in a DOCSIS network while utilizing conventional cable modem termination system (CMTS) equipment. A cable modem system in accordance with the invention includes a cable modem and a CMTS adapted to send and receive compressed payload data. In one example, the cable modem is adapted to compress PDU payload data using a data compression dictionary and the CMTS is adapted to reconstruct the compressed PDU payload data that is received from the cable modem.

Abstract: A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth.

Abstract: A low-noise transmitter architecture and method for high linearity, high output-swing systems such as Asymmetrical Digital Subscriber Line (ADSL) systems. The transmitter uses a switched-current DAC having a current source coupled to ground, followed by a current-to-voltage converter. The resistance of the current source is typically large enough so that noise from an op-amp included in the current-to-voltage converter is not significantly amplified at the output. The current source may be passive and may include at least one resistor connected to ground. With a passive current source, portions of a signal output by the DAC enter either the current source or the current-to-voltage converter, but not both, eliminating noise in the system produced by the current source.

Abstract: The present invention relates to battery chargers. A first controller can be configured to set, when a first power supply is coupled to a first port, a current produced by a variable current source at a safe rate to charge a battery. An ammeter can be configured to measure, when the battery is coupled to a second port, the current flowing into the battery. The first controller can be configured to increase, after a passing of a quantifiable amount of time, the current produced by the variable current source by a quantifiable amount of current. The first controller can be configured to continue iteratively to increase, after the passing of the quantifiable amount of time, the current produced by the variable current source by the quantifiable amount of current until the safe rate is near or at a highest safe rate to charge the battery.

Abstract: A distribution server includes a communication interface, storage, and processing circuitry. The processing circuitry retrieves a full screen sequence of video and sub-frame metadata relating to the full screen sequence of video. The processing circuitry sub-frame processes the sequence of full screen video using the sub-frame metadata to produce a plurality of sub-frames of video. The processing circuitry assembles the plurality of sub-frames of video to produce an output sequence for a client system. The distribution server may also receive, store, and distribute the sub-frame metadata and/or the video for subsequent use by a video processing system.

Abstract: A removable storage media is received by and interacts with both a first video player system and a second video player system. The first video player system has a first video display that has a first display characteristic and the second video player system has a second video display that has a second display characteristic, the first display characteristic being different from the second display characteristic. The removable storage media includes a plurality of storage locations and stores a sequence of full frames of video data, first sub-frame metadata, and second sub-frame metadata. The first sub-frame metadata is generated and the second sub-frame metadata are used to process the full frames of video data to correspond to the first video display and the second video display, respectively.

Abstract: A flip chip package generally includes a substrate, a flip chip die, and a heat spreader. The flip chip die is coupled to the substrate. The heat spreader is coupled to the flip chip die. The heat spreader can include one or more walls. Generally, the one or more walls at least partially laterally surround the flip chip die and/or the substrate. The walls can completely laterally surround the flip chip die to define a cavity in the heat spreader. The flip chip package can further include an encapsulate. For example, the encapsulate can be injected between the one or more walls of the heat spreader and the flip chip die and/or other components of the flip chip package. The encapsulate and/or the one or more walls of the heat spreader can protect one or more components of the flip chip package against moisture, corrosives, heat, or radiation, to provide some examples.

Abstract: A receiver architecture for canceling blocking signals in the receive path includes a low noise amplifier for receiving and amplifying an inbound RF signal to produce an amplified inbound signal, in which the inbound RF signal includes a modulated RF signal and a blocking signal, and a cancellation module for substantially canceling the blocking signal from the amplified inbound RF signal and substantially passing the modulated RF signal. The cancellation module cancels the blocking signal by generating an injection signal representative of the blocking signal, combining the blocking signal with the injection signal to produce an error signal, updating the injection signal based on the error signal and using the injection signal to cancel the blocking signal from the amplified inbound RF signal.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Abstract: A method for avoiding signal interference between a first RF device and a second RF device is provided. The first and second RF devices are co-located and the first RF device is configured to operate within a semi-stationary range of a frequency band. The second RF device is configured to operate by changing channels within the frequency band. The method initiates with a communication interface being provided between the first RF device and the second RF device. Then, the second RF device receives the semi-stationary range and a mode for the first RF device through the communication interface. Next, the second RF device is adapted to avoid the semi-stationary range of the frequency band of the first RF device when the mode of the first RF device is in an active mode. An apparatus where two RF devices are co-located without causing interference for each other is also provided.

Abstract: Carrier signals modulated by information (video and/or data) signals are received through a cable and are converted to modulated signals at an intermediate frequency. The IF signals are sampled at a particular frequency to produce digital information signals. The digital information signals are introduced to a variable interpolator which produces first digital signals. The first digital signals are introduced to a complex multiplier which produces second digital signals. The second digital signals pass to an adaptive equalizer which selects for each of the second signals in accordance with the amplitude of such second signals, an individual one of a multitude of amplitude levels involved in quadrature amplitude modulation. These selected amplitude levels represent the information (video and/or data). The output signals from the adaptive equalizer are introduced to a first signal recovery loop which includes a first numerically controlled oscillator.

Abstract: A digital modulator includes a quantizer and a mapper. The quantizer converts a dithered signal value to a voltage. The mapper provides a modulated signal based on the voltage received from the quantizer. The mapper may maintain a substantially identical average centroid for modulated signals provided by the mapper. In an aspect, the mapper is included in a feedback of the digital modulator. The digital modulator may include any number of mappers. For example, a mode selection switch may select one of a plurality of mappers to map a voltage level received from the quantizer to a respective digital sequence.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: Present herein is a system and method for arbitration in multi-threaded programming. Task calls are directed to a task wrapper that associates the task call with a particular unique identifier, and stores parameters provided by the task call at memory locations associated with the unique identifier. The execution of the task is handled by a task loop. The task loop queues a plurality of memory portions into a circular queue. The contents of the queue are serially provided to the task, and the results are serially written to the circular queue and provided back to the calling threads.

Abstract: A method for debugging a ROM in a wireless target device. After a wireless communication link is established with the target device by a host computer, a debug mode change command is transmitted to the target device by the host computer. The debug mode change command is received by the target device and a monitor program is enabled to parse the serial port. A debug instruction from a debugger in the host computer is then received by the monitor program where, the debug instruction includes an entry address and a jump address. The application program jumps to the received jump address upon reaching the entry address location in the application program. An acknowledgement package is transmitted to the debugger in the host computer, and a second debug instruction is received from the debugger, responsive to the acknowledgement package.

Abstract: A method and system of the present invention includes the creation and transmission of a MAC header that includes a first MAC header portion and at least two scrambler recovery fields arranged on the two sides (before and after) of a header FEC portion. The invention includes determining whether a scrambler initialization field received at the physical layer was received in error, and if so, evaluating either one of the de-scrambled values of the two scrambler recovery fields in relation to a table to determine a pseudorandom sequence initialization value that corresponds to a given de-scrambled scrambler recovery field value. Once the corresponding pseudorandom sequence initialization value is determined, that value may be used to further de-scramble the data in the data frame to produce a correctly de-scrambled data frame.

Abstract: In the current invention, a method and apparatus for automatically managing fragmentation on a disk is described. This is done by having a special inode for preallocation and dumping of contiguous block chunks.

Abstract: A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In a computing environment made up of one or more personal computing devices (PCD) and/or one or more powered devices (PD), power source equipment (PSE) determines an allocated amount of power to be supplied to each device. The personal computing devices include a unified LAN-On-Motherboard (LOM) that combines the functionality of a powered device (PD) controller of a conventional PD and a LOM of a conventional personal computing device into a single unified subsystem. This allows the personal computing devices to use the existing hardware architecture and software architecture, such as software drivers and Access Protocol Interfaces (API), with few modifications to implement PoE.