Abstract: A scheme in which a first decoder provides first decoding of a signal read from a disk. A second decoder, coupled to an output of the first decoder, combines with the first decoder to provide iterative decoding to recover data stored on the disk when in an iterative mode of operation. However, when in a non-iterative mode of operation, the output of the first decoder is coupled to an error correction code module to apply error correction code (ECC) to the output of the first decoder to recover data stored on the disk by non-iterative decoding.

Abstract: Video player circuitry used with encoded source video and a display. Decoder circuitry receives encoded source video and decodes the encoded source video to produce a sequence of full frames of video data. Pre-processing circuitry, pursuant to sub-frame information, generates a plurality of sequences of sub-frames of video data from the sequence of full frames of video data, a first sequence of the plurality of sequences of sub-frames of video data having a different center point within the sequence of full frames of video data than that of a second sequence of the plurality of sequences of sub-frames of video data. Post-processing circuitry, pursuant to supplemental information, modifies the plurality of sequences of sub-frames of video data to produce an output. Interface circuitry that delivers the output for subsequent presentation on the display.

Abstract: A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit configured to extract a plurality of bit fields from a source reservoir and to populate a plurality of destination lanes in response to a single instruction. In addition, the execution unit is configured to write supplied fill data into the source reservoir if the number of bits in the source reservoir is less than a predetermined number. In addition or alternatively, the system may include at least one execution unit configured to combine a plurality of bit fields from a plurality of source lanes into a continuous bit stream in response to a single instruction executable by the processor.

Abstract: A chip comprises and operational section and an input/output section. The operational section includes a controller. The input/output (I/O) section is coupled to the operational section. The I/O section comprises a transformer and a switching device. The transformer includes a primary side connected to first and second I/O ports and a secondary side connected to the operational section. The switching device is coupled to the controller and between the first and second I/O ports and a bias port, such that, under control of the controller, the switching device connects one of the first and second I/O ports to the bias port.

Abstract: A method, system, and computer program product for ordering grants of upstream bandwidth in a two-way grant-based communication system, such as a DOCSIS-based communication system. Typically, a central controller, such as a CMTS, sends a grant message to a set of end user devices, e.g., cable modems, wherein the message defines when each end user device can transmit upstream. The invention first determines, for each end user device, the time needed for processing the grant message. The central controller then constructs the grant message, such that grants for the end user devices associated with the shortest grant message processing times occur early in the grant message and represent the earliest grants. Grants for end user devices associated with the longest grant message processing times occur later in the grant message and represent later grants.

Abstract: Virtual disk drive architecture. A novel approach is presented by which a virtual design system allows for the design, development, and testing of memory storage devices including hard disk drives (HDDs). A virtual disk drive architecture allows for the implementation and emulation of a full HDD system. All of the pieces of the HDD system (e.g., including both the read channel and the controller functionalities) are included and implemented to allow a designer to develop and test certain portions within the system. In some embodiments, one or more field programmable gate arrays (FPGAs) are employed to implement a hard drive (HD) controller in an all digital implementation. Various combinations including circuit boards and FPGAs can be employed to emulate an entire HDD system. In even other embodiments, one or more sockets, and appropriate interfacing, are included to allow the testing of actual chips within the virtual disk drive architecture.

Abstract: Upstream requests such a bandwidth requests, are processed by CMTS out of order on a priority basis to reduce latency in responding to the request. Specifically, a cable modem termination system (CMTS) is connected to a plurality of cable modems by a cable plant. The CMTS has a burst receiver adapted to be connected to the cable plant to process upstream data packet units and bandwidth requests transmitted by the cable modems. Each packet includes a header that uniquely distinguishes the bandwidth requests from other data types. Packet data units are arranged in a first memory queue. Bandwidth requests are arranged in a second memory queue. The headers of the packets processed by the burst receiver are inspected as they arrive at the CMTS to determine if the packets are packet data units or bandwidth requests. Packet data units are routed to the first memory queue. Bandwidth requests are routed to the second memory queue.

Abstract: Physical layer (PHY) sub-channel processing. A soft symbol decision stream is arranged into a number of sub-channels to reduce substantially the processing performed within a communication receiver on data that is not intended for that communication receiver. In other embodiments, a predetermined approach is employed to arrange the soft symbol decision stream into one or more frames; each frame may have one or more soft symbol blocks; and each soft symbol block may have one or more symbols. Each of the soft symbol blocks, within a frame, may be assigned to a sub-channel. Only the soft symbol blocks that contain information destined for the communication receiver need be decoded. Only the sub-channel that includes these soft symbol blocks, destined for this communication receiver, need be decoded. The soft symbol blocks not within the sub-channel may be discarded thereby recovering some of the processing capabilities of the communication receiver.

Abstract: A Wireless Local Area Network (WLAN) system in which wireless terminals each operate upon battery power. One of the wireless terminals acts as a Master to coordinate the transmission and receptions of the Slaves so as to reduce the power consumed by all of the devices. The Slaves operate according to a power up and power down sequence to conserve battery power. Further, the terminals may alternate between being Slaves and being the Master to equalize battery consumption of the wireless terminals.

Abstract: Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface may be made such that the ground and VDD potential levels are effectively brought onto the die of the chip such that a true ground potential is maintained within the chip. This off-chip LC circuit operates cooperatively with an on-chip decoupling capacitor to reduce the overall effective inductance of the bond wires employed to bring signal and voltage levels from the die to the chip exterior. This circuit ensures a relatively low impedance for a PA (Power Amplifier) that is implemented within chip thereby providing for improved performance.

Abstract: A dual mode clock for providing first and second clock signals to a wireless interface unit. The first and second clock signals correspond to first and second operating states of the wireless interface unit. In the first operating state, the transceiver in the RF analog module is operational and the clock generator provides a first clock signal having low phase-noise characteristics necessary to maintain efficient operation of the transceiver. In a second operating state, the transceiver in the RF analog module is turned off. In this second operational state, the clock generator provides a second clock signal having a quality sufficient to maintain efficient operation of the digital baseband module in the wireless interface.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

Abstract: An aspect of the invention provides for recovering communicated information in a communication system. Recovering communicated information in a communication system may include generating a first digital signal from a received analog signal bearing communicated information, the first digital signal having a pre-cursor response and a post-cursor response. A second digital signal may be generated that limits a duration of at least a portion of the post-cursor response and a third digital signal may be generated that inhibits at least a portion of the pre-cursor response. A fourth digital signal that inhibits at least a portion of the post-cursor response and a fifth digital signal that limits a duration of at least a portion of the fourth signal may be generated in order to recover the communicated information. A sixth digital signal based on at least the third digital signal and the fifth digital signal may be generated.

Abstract: A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second demultiplexer receives an output of the second flip flop and outputs zero data. A timing recovery circuit outputs phase control bits based on the zero data and the peak data. A first phase interpolator outputs the 0° clock based on the phase control signal. A second phase interpolator outputs the 180° clock based on the phase control signal. A phase register receives the phase control signal from the timing recovery circuit. The first and second flip flops can be D flip flops. The first and second phase interpolators adjust relative phases of the 0° clock and 180° clock based on the phase control signal.

Abstract: Determination of variable code rates for a rate control sequence. A rate control sequence governs symbols that are to be encoded and/or decoded. A different rate control value may be used to control code rates of individual symbols in a signal. The determination of the variable code rates may be performed based on a number of parameters including a communication system's operating conditions and/or the signal to noise ratio (SNR) of a communication channel. The variable code rates may also adaptively change, in real time (if desired), in response to the communication system's operating conditions including a communication channel's SNR. The variable code rate functionality may also be adaptively tailored to match the SNR of a communication receiver's communication channel within a multi-receiver communication system; those receivers in a beam spot (higher SNR) may operate using a higher code rate than those receivers further away from the spot (lower SNR).

Abstract: Provided is a system and method for muting zero level pulse code modulated (PCM) samples. PCM samples are received as inputs to a digital to analog converter (DAC) including a PCM input module and a mapping module. The method includes monitoring a level of the PCM samples received as inputs to the PCM input module and sensing consecutive zero level PCM samples from among the monitored input PCM samples. The method also includes muting a PCM input to the mapper when a predetermined number of zero level PCM samples have been sensed.

Abstract: A system and method are disclosed for efficiently performing multiplication of an input vector and an input matrix having a limited number of possible values for any element of the input matrix. Elements of the input matrix are grouped across a second dimension of the input matrix to form groups of matrix elements. All possible permutations of partial results for each of the groups of matrix elements are pre-computed. The partial results from each of the groups of matrix elements are assigned to each of a corresponding index of a first dimension of the input matrix to form a matrix of assigned partial results. The assigned partial results are summed along the first dimension of the matrix of assigned partial results to form a vector of full matrix multiplication results.

Abstract: LDPC (Low Density Parity Check) coded modulation symbol decoding using non-Gray code maps for improved performance. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. In addition, the LDPC coded modulation symbol decoding can be employed to decode a signal that has been encoded using LDPC-BICM (Low Density Parity Check-Bit Interleaved Coded Modulation) encoding with non-Gray code mapping. By using the non-Gray code mapping, a performance improvement over such a system using only Gray code mapping may be achieved.

Abstract: A programmable channel-swap crossbar switch for swapping signal flow from one channel to another within an Ethernet physical layer device (PHY) is presented. The crossbar switch includes two or more programmed multiplexers, each multiplexer configured to receive two or more input signals and to select which one of the input signals to pass to a programmed corresponding channel, such that a first input signal associated with a first channel can be swapped to a second channel as operating conditions necessitate. The crossbar switch can be used for Ethernet communications with various communication speeds, such as 10BaseT, 100BaseT, and Gigabit communications. A crossbar switch can be used in both a transmit path and a receive path. Two crossbar switches may be used in a receive path in order to undo channel swapping for control signal processing. A method of channel-swapping in an Ethernet PHY communications system is also presented.

Abstract: The radio frequency integrated circuit (RFIC) electrostatic discharge (ESD) circuit includes an integrated circuit pad and a radio frequency (RF) ESD circuit. The integrated circuit pad provides coupling to an antenna. The RF ESD circuit is coupled to the integrated circuit pad, wherein the RF ESD circuit provides ESD protection at the integrated circuit pad, provides coupling of inbound RF signals from the antenna to low noise amplifier, and provides coupling of outbound RF signals from a power amplifier to the antenna.