Abstract: A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In a computing environment made up of one or more personal computing devices (PCD) and/or one or more powered devices (PD), power source equipment (PSE) determines an allocated amount of power to be supplied to each device. The personal computing devices include a unified LAN-On-Motherboard (LOM) that combines the functionality of a powered device (PD) controller of a conventional PD and a LOM of a conventional personal computing device into a single unified subsystem. The unified LOM includes a standard or universal interface between the LOM and PD controller so that different types of PD devices with differing functionality can be easily married to the LOM, without requiring significant hardware or software redesign.

Abstract: New version packet data devices support a backwards-compatible signal format. New version devices operate within a first frequency band while old version devices operate within a second frequency band. The first frequency band differs from but overlaps with the second frequency band. The new version devices may operate on a first carrier frequency (within the first frequency band) while old version devices may operate at a second carrier frequency (within the second frequency band). The new version devices and/or the old version devices may also support carrier-less modulations. Preamble, header, and trailer portions of a new version signal include a plurality of spectral copies of a baseband modulated signal. One or more of these spectral copies of the baseband modulated signal is/are indistinguishable from corresponding components of an old version signal. The payload of the new version signal may be formed in the same manner or may be formed in have a wider bandwidth, higher data rate format.

Abstract: A system and method for encoding and decoding speech signals that includes a specially-designed Code Excited Linear Prediction (CELP) encoder and a vector quantization (VQ) based Noise Feedback Coding (NFC) decoder or that includes a specially-designed VQ-based NFC encoder and a CELP decoder. The VQ based NFC decoder may be a VQ based two-stage NFC (TSNFC) decoder. The specially-designed VQ-based NFC encoder may be a specially-designed VQ based TSNFC encoder. In each system, the encoder receives an input speech signal and encodes it to generate an encoded bit stream. The decoder receives the encoded bit stream and decodes it to generate an output speech signal. A system and method is also described in which a single decoder receives and decodes both CELP-encoded audio signals as well as VQ-based NFC-encoded audio signals.

Abstract: A technique is provided for automatically adjusting the volume, or magnitude, of an audio signal. The technique includes calculating an average power associated with a segment of an input audio signal, determining whether the average power is greater than an estimated signal level associated with one or more previously-processed segments of the input audio signal and, depending on the determination, either calculating an updated estimated signal level by subtracting from the average power an attenuated difference between the estimated signal level and the average power or setting the updated estimated signal level to the average power. A gain to be applied to the segment of the input audio signal is then determined based on the updated estimated signal level and a target signal level for an output audio signal.

Abstract: A method for synchronizing counters in a wireless terminal device with those of an administrative device. A wireless terminal device advances its frame counter. With each increment of the frame counter, the wireless terminal device minislot counter advances by an amount equal to the number of minislots per frame. Likewise, with each increment of the frame counter, the wireless terminal, device's timestamp counter is incremented by the number of timestamps per frame. This continues until the counters at the wireless terminal device are within one frame of the administrative device's counters. The minislot counter is then incremented. With each increment of the minislot counter, the timestamp counter is incremented by an amount equal to the number of timestamps per minislot. This continues until the wireless terminal devices counters are within a minislot of the administrative device's counters.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: The present invention provides a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked ioop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract: A system and method for encoding dynamic image information for an image generated by a computer application executing on a processor. Various aspects of the present invention may comprise determining a first set of information describing a reference image. A second set of information may be determined for describing an image, wherein the second set of information comprises information indicative of movement between the image and the reference image. For example, a set of primary movement directions may be determined based at least in part on the computer application generating the image. Such set of primary movement directions may be utilized for analyzing the image relative to the reference images. The difference between the image and the reference image may, for example, be analyzed using at least one of the set of primary movement directions. A movement direction may, for example, be utilized to describe the image.

Abstract: A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.

Abstract: A system and method for synchronizing signals having respective sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal with an associated sub-carrier. Various aspects may determine a phase of the sub-carrier and store an indication of such phase. Various aspects may generate and store a cropped version of the sampled signal. Various aspects may also store an indication of which samples were cropped from the sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may read a cropped version of a sampled signal and an associated indication of phase. Various aspects may generate a restored sampled signal by adding samples to the read cropped version. Various aspects may, based on the synchronization signal and indication of phase, output the restored sampled signal aligned with a second sampled signal.

Abstract: High precision continuous time gmC BPF (Band Pass Filter) tuning. A novel approach is presented by which a continuous time signal serves as a BPF control voltage for tuning of a BPF within a communication device (e.g., transceiver or receiver). A PLL (Phase Locked Loop) tunes the center frequency of the BPF using this continuous time signal, and the PLL oscillates at the center frequency of the BPF. The BPF is implemented as a gmC (transconductance-capacitance) filter, and the PLL is implemented using a number of gm (transconductance) cells as well. The PLL's gm cells and the BPF's gm cells are substantially identical in form. All of these gm cells are operated within their respective linear regions. This similarity of gm cells within the PLL and the BPF provide for substantial immunity to environmental perturbations including temperature and humidity changes as well as fluctuations of power supply voltages.

Abstract: A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to strobe in data bits and output a pair of data bits onto the internal bus each half clock cycle.

Abstract: A data aligner aligns a data segment having a granularity of less than a width of an internal data path. The data aligner aligns a fragment of data for alignment with a current segment or delay the fragment to combine with a next segment for alignment of data. A buffer receives the aligned data from the data aligner for interim storage and subsequent output onto an internal data path.

Abstract: A receiver architecture for canceling blocking signals in the receive path includes a low noise amplifier for receiving and amplifying an inbound RF signal to produce an amplified inbound signal, in which the inbound RF signal includes a modulated RF signal and a blocking signal, and a cancellation module for substantially canceling the blocking signal from the amplified inbound RF signal and substantially passing the modulated RF signal. The cancellation module cancels the blocking signal by generating an injection signal representative of the blocking signal, combining the blocking signal with the injection signal to produce an error signal, updating the injection signal based on the error signal and using the injection signal to cancel the blocking signal from the amplified inbound RF signal.

Abstract: A technique to perform a guided partial response target search for characterizing a read channel of a disk drive. A target adaptation scheme pre-selects a plurality of targets from a pool of potential targets based on certain criteria and the selected targets are sorted in linear gradient orders. When target adaptation is being performed by comparing the equalizer output with an ideal reconstructed signal, a difference value sets a gradient vector that is used to determine which direction to move along the sorted list of targets to select the next target.

Abstract: A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.

Abstract: A controller is disclosed that can be used in controlling a drive device of a disk drive, or other systems, in the presence of sinusoidal disturbances. The controller includes a calibration module that generates a plurality of reference states for a reference region of a disk of the disk drive. An initialization state generation module generates a plurality of initialization states for at least one other region of the disk as a function of the plurality of reference states, a displacement between the other regions of the disk and the reference region of the disk, and a reference state transition matrix. A control module generates a control signal for the drive device based on the plurality of initialization states.

Abstract: A technique to sample a signal from a disk by using frequency and phase offset adjustment in a phase locked loop (PLL) timing recovery loop to sample read data from the disk, prior to a disk clocked clocking acquires a lock. Subsequently, sampling a signal from a disk by using only phase offset adjustment in the PLL timing recovery loop to sample read data from the disk after the disk clocked clocking acquires the lock. The sampled data is then error corrected by applying an error correction code (ECC).

Abstract: The present invention relates to a transceiver for bidirectional frequency division multiplexed transmission, a communication system including one or more transceivers. Optionally, the communication system is a communication system for a digital subscriber line. The transceiver comprises transmission means with a voltage source output or a current source output for transmitting data in a transmission frequency range, receiving means for receiving data in a receiving frequency range, and a coupling impedance for connecting the transmission means and the receiving means to a transmission medium. The magnitude of the coupling impedance in the transmission frequency range is smaller than the magnitude of the coupling impedance in the receiving frequency range if the transmission means has a voltage source output and is higher than the magnitude of the coupling impedance in the receiving frequency range if the transmission means has a current source output.