Abstract: A method for reducing the bandwidth required to transmit a data packet via a wireless network is provided. In an embodiment, the method includes generating a packet to be transmitted via the wireless network. Once a packet is generated, a packet a packet type of the packet to be transmitted via the wireless network is determined. Based on the packet type, a suppression rule is selectively applied to the packet to generate a suppressed packet. Applying the suppression rule includes suppressing at least a portion of the header of the packet and adding a descriptor associated with the header suppression rule to the packet. The method concludes with the transmittal of the suppressed packet via the wireless network.

Abstract: An input inductor or input inductive network is used to improve the performance of circuits working in discrete time domain, especially a sample and hold circuit. Input series inductors resonate with the capacitance at the input of the sample and hold at high frequencies to extend its bandwidth. At high frequencies, the inductors act as high impedance chokes between the termination resistor and the capacitors and thus also improve the input reflection of the chip.

Abstract: A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In an enterprise environment made up of one or more personal computing devices (e.g., personal or laptop computers), a switch determines a power classification for each device via a PoE control module that can be part of, for example, a Power Source Equipment/Powered Device (PSE/PD) system or a LAN-On-Motherboard/Powered Device (LOM/PD) system. A method of classifying power for each device includes detecting a device, polling it for power requirement information using a Layer 2 data link layer, receiving power requirement information from the device, and determining a power classification for the device. Power requirement information can include battery charge status, power load, power mode, etc., of the device. Various types of data packets can be used. The method can be repeated on a periodic basis, allowing power classification to be dynamic.

Abstract: A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In an enterprise environment, a table top network switch uses a power supply to provide power for PoE and data communications to one or more powered devices (e.g., personal or laptop computers). To reduce the amount of heat generated in the table top network switch, the power supply is located external to the table network switch. The table top network switch may also include enterprise equipment, such as a video projector, a monitor for a personal computing device, another personal computing device to provide some examples. The power supply for the enterprise equipment may be included within the table top network switch to provide additional integration. The power for PoE and data communications to a limited number of powered devices (e.g., personal or laptop computers) may be included within the table top network switch to provide even further integration.

Abstract: A system and method for providing dynamic allocation of MIMO communication resources during a single communication. Various aspects of the present invention may comprise determining a first set of MIMO communication resources to utilize for communicating a first portion of a unit of information. The first set of MIMO communication resources may be allocated for communicating the first portion of the unit of information. A second set of MIMO communication resources may be determined to utilize for communicating a second portion of the unit of information, where the second set of MIMO communication resources is different from the first set of MIMO communication resources. The second set of MIMO communication resources may be allocated for communicating the second portion of the unit of information. The first and second portions of the unit of information may, for example, be communicated consecutively or concurrently.

Abstract: A low profile Planar Inverted-F Antenna (PIFA) comprises a radiating strip, an inductive tuning portion, a vertical feed portion, and a retracted ground plane. The radiating strip is approximately parallel to the ground plane and is suspended above the ground plane by the feed element at a certain distance. Further, the radiating strip, in part or entirely, overhangs the ground plane. In this way, the radiating strip may be suspended very close to the ground plane, but yet exhibits a large bandwidth.

Abstract: An interface which effects communication between first and second systems and includes a first arrangement for communicating with the first system using a first protocol and a second arrangement for communicating with the second system using a second protocol. At least one of the arrangements includes a mechanism for effecting wireless communication. In accordance with the invention, a third arrangement is included for translating data received from the first system in accordance with the first protocol into data adapted for the second system in accordance with the second protocol. In the illustrative embodiment, the inventive interface further includes an arrangement for translating data received from the second system in accordance with the second protocol into data adapted for the first system in accordance with the first protocol.

Abstract: Timing recovery optimization using disk clock. A novel means is presented to perform and provide control of the sampling frequency of a signal that is read from a disk within a hard disk drive (HDD). Two separate, yet somewhat cooperating control loops are employed to provide feedback control of the sampling frequency of the signal that is read from disk. A timing recovery loop and a disk clock loop operate in conjunction with one another according to some desired manner (which can be predetermined or adaptive) to ensure that the sampling of the signal is performed to a very accurate degree. In one implementation, the timing recovery loop governs the sampling rate until the disk clock loop has locked, from which time either the disk clock loop govern the sampling or some combination of the signals provided from the two loops govern the sampling.

Abstract: A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.

Abstract: LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until a sufficient degree of precision is achieved. The symbol node updating of the bit edge messages involves using symbol metrics corresponding to the symbol being decoded as well as the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages involves using the bit edge messages most recently updated by symbol node updating. The symbol node updating also involves computing possible soft symbol estimates for the symbol during each decoding iteration.

Abstract: Hard disk controller having multiple, distributed processors. A novel approach is presented by which a separate and dedicated processor is provisioned to service each of a plurality of control loops within a hard disk drive (HDD) controller. For example, a first processor is implemented to service a servo control loop, a second processor is implemented to service channel interfacing, and a third processor is implemented to service host interfacing. In some embodiments, the channel and host interfacing are performed using protocol processors implemented within each of a disk manager module and a host manager module, respectively.

Abstract: A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In an enterprise environment made up of one or more personal computing devices (e.g., personal or laptop computers), a switch determines an allocated amount of power to be supplied to each device. The system includes a switch, a power supply, and one or more personal computing devices having a PoE control module. The PoE control module can be part of, for example, a Power Source Equipment/Powered Device (PSE/PD) system or a LAN-On-Motherboard/Powered Device (LOM/PD) system. A method of dynamically providing power to personal computing devices includes determining the power requirements of each device based on one or more factors, which can include, for example, battery charge status, power load, power mode, etc., of each device. Various algorithms can be used to decide priority in providing power to the devices.

Abstract: Hard disk drive progressive channel interface. A novel approach is presented by which the interface between a channel circuitry and a controller circuitry, such as those which can be implemented within a hard disk drive (HDD). Because of the location in which the disk management operations are supported and performed within the channel circuitry, the interface between the channel circuitry and the controller circuitry can be implemented to support direct memory access (DMA) protocol data transfers and control there between. Because the disk management operations are supported within the channel circuitry, as opposed to the controller circuitry, then the disk management operations need not necessarily comply with an interface between the channel circuitry and the controller circuitry. This allows for better control of the disk management operations as well as a much broader range and type of interface that can be employed for the interface between the two circuitries.

Abstract: In the current invention, a method and apparatus for efficiently deleting large files is described. This is done by having a special inode for pointing to data blocks to be freed, and subsequently freeing the data blocks from the special inode in a controlled manner.

Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: A connector device (for example, a jack) is provided with a sensing mechanism that detects mating of another connector to the connector device, and differentiates between matching and non-matching connectors. The sensing mechanism generates a signal to indicate that a non-matching connector has been mated with the connector device.

Abstract: A method of forwarding data in a network switch fabric is disclosed. An incoming data packet is received at a first port of the fabric and a first packet portion, less than a full packet length, is read to determine particular packet information including an opcode value. The opcode value allows the fabric to determine the packet type, such a a whether the packet is a broadcast packet, a unicast packet, a multicast packet, etc. Based on the opcode value read, a particular forwarding table of a plurality forwarding tables is read and an egress port bitmap is determined based on entries read from the particular forwarding table. The incoming data packet is then forwarded based on the egress port bitmap. In addition, the architecture of the switch fabric is also disclosed.

Abstract: A shared buffer packet switching device is provided for receiving data packets via associated ones of a plurality of receive ports, and for transmitting data packets via associated selected ones of a plurality of transmit port.

Abstract: An encoder includes a state machine configured to generate a payloads as a function of a state machine output, and an interface configured to generate a tail as a function of a binary representation of the state machine output at the end of the payload generation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A system and method is provided for scheduling transmissions from a plurality of services operating over a widely distributed communications network. A headend communications device (such as a cable modem termination system) arbitrates bandwidth among a plurality of cable modems configurable for bidirectional communications. The headend grants a bandwidth region to a specified cable modem or assigns contention regions for a group of cable modems. Each cable modem contains a local scheduler that sends requests for bandwidth according to local policies or rules. Upon receipt of a grant from the headend, the local scheduler selects packets to be transmitted to best serve the needs of the services associated with the cable modem. Accordingly, a service requesting bandwidth may not be the service utilizing the grant corresponding to bandwidth request.