Abstract: A method is used that substantially simultaneously trellis encodes data to be modulated onto multiple tones. The embodiments of the present invention comprise the steps of: (a) using a first input operand comprising state bits for a first trellis stage; (b) using a second input operand comprising a plurality of input data bits; and (c) generating an output comprising output data bits and output state bits from a first or later trellis stage.

Abstract: An apparatus and method for a wire-bond die-up area array package is described. The package includes an integrated circuit (IC) die, a substrate, and a thermally conducting body. A bottom surface of the IC die is exposed through an opening in a central region of the substrate. The die is mounted to the thermally conducting body. A bottom surface of the thermally conducting body is configured to be connected to a circuit board, such as a PWB, when the package is mounted to the circuit board. The bottom surface of the thermally conducting body may be connected directly to the circuit board, or may be coupled to the circuit board via solder balls or other mechanism. One or more wirebonds are used to electrically connect the die to a top surface of the substrate. A mold compound encapsulates the die, the wirebonds, and at least a portion of the top surface of the substrate, and fills a gap between peripheral edges of the IC die and inner walls of the substrate central window opening.

Abstract: An integrated multimode radio includes a multimode receiver and a multimode transmitter. The multimode receiver includes a shared receiver front-end, a receiver multiplexor, and a plurality of receiver IF stages. The multimode transmitter includes a shared transmitter front-end, a transmitter multiplexor, and a plurality of transmitter IF stages.

Abstract: A high efficiency class-AB amplifier is disclosed. The amplifier comprises a first input stage and a second input stage, both coupled to a class-AB biasing mesh and an output stage, wherein the outputs of the first and second input stages are directly coupled to the output transistors in the output stage. In one embodiment, a first gate of the first input stage and of the second input stage are coupled together to receive the same input and a second gate of the first input stage and of the second input stage are coupled together to receive the same input. In another embodiment, the first input stage and second input stage may further comprise cascode transistors for coupling the two input stages to the class-AB biasing mesh. In yet another embodiment, a 3V supply is used and 1V transistors are used to improve gain and 3V transistors are used to protect the 1V transistors.

Abstract: A line driver for generating 10 BT signals is disclosed. Digital symbols to be transmitted via a 10 BT Ethernet line are converted by a digital-to-analog converter into a corresponding analog voltage signal, which is fed into an active output impedance line driver. The digital-to-analog converter also receives a reference voltage reflecting variations of the supply voltage and adjusts its output signal accordingly to provide a deliberately variable analog voltage signal to the line driver.

Abstract: A power amplifier for use in a transmitter includes a first transistor having an input, a first node and a second node, a second transistor having an input, a first node and a second node and a digital to analog conversion module. The input of the first transistor is operably coupled to receive a first input, while the input of the second transistor is operably coupled to receive a second input. The second nodes of the first and second transistors provide an output of the power amplifier. The digital to analog conversion module is operably coupled to control current through the first and second transistors based on at least one of a power control signal and an amplitude modulation control signal.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB) or the communication ASIC to another communication ASIC. The high-speed bit stream interface includes a plurality of signal conditioning circuits. The signal conditioning circuits service each of an RX path and a TX path and include a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

Abstract: Aspects of a method and system are provided for error detection for improving data integrity in protocol offloading. Aspects of the invention may enable receiving a block of data having a modulo-based input error detection code and an error correction term appended thereto, calculating an output error detection code of the block, combining the input error detection code and the error correction term to produce a modified error detection code, and comparing the calculated error detection code to the modified error detection code so as to detect an error in the block. The error correction term may be equal to a binary difference between the input error detection code and the output error detection code. The input error detection code and the error correction term may be combined by applying an XOR operation.

Abstract: Apparatuses, methods, and systems for improved integrated circuit packages are described. An integrated circuit (IC) package includes a substrate having opposing first and second surfaces, an IC die, a plurality of conductive elements, and an encapsulating material. The substrate has a plurality of contact pads on the first surface that are electrically coupled to a plurality of electrically conductive features on the second surface. The plurality of conductive elements is formed on the first surface of the substrate. The IC die is located on the first surface of the substrate. The encapsulating material encapsulates the IC die and a portion of each element of the plurality of conductive elements.

Abstract: A method and apparatus for channel estimation in a spread spectrum receiver include processing that begins by despreading a received spread spectrum complex baseband sample utilizing a pseudorandom spreading sequence to produce a despread baseband symbol. The processing continues by filtering the despread baseband symbol to attenuate adverse channel effects based on a channel response estimate to produce a filtered despread baseband symbol. The processing then continues by decoding the filtered despread baseband symbol to produce recaptured data. The processing continues by modulating the recaptured data to produce a remodulated symbol. The processing then continues by producing a reconstructed spread spectrum complex baseband sample from the remodulated symbol based on the pseudorandom spreading sequence.

Abstract: A method and related computer program product for combining resources of multiple RAID controllers and managing them as a single entity, comprising searching the RAID controllers for the most appropriate version of the firmware to be executed, determining whether a more appropriate version of the firmware was previously loaded into system memory, unloading inappropriate versions of the firmware, loading the most appropriate version of the firmware and initializing all RAID controllers as a commonly managed entity having combined resources.

Abstract: A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

Abstract: Digital signal processing for television signals includes digital feedback loops. Analog information signals are oversampled to provide digital signals. The digital signals are introduced to a digital carrier recovery loop and a digital symbol recovery loop. The gain of the digital signals is also regulated in a feedback loop. The digital signals are processed to recover the data in the data signals. The use of digital feedback loops allows information recovered from the digital signals to be precise. Carrier signals can be directly demodulated to produce baseband inphase and quadrature signals, or first downconverted to produce intermediate frequency signals.

Abstract: A communication system includes an integrated circuit (IC) die having an on-chip source termination. The on-chip source termination can be a non-precision resistor, such as an unsilicided poly resistor, or any other suitable termination. As compared to an off-chip source termination, the on-chip source termination can reduce voltage peaking and/or voltage overshoot in the IC die and/or at a load that is connected to the IC die. The IC die can further include a line driver to provide a source current. A bias generator can be included to provide a bias current to the line driver. The bias generator can include a first current source coupled to an off-chip resistor and a second current source coupled to an on-chip resistor. An output voltage of the IC die can be adjusted by manipulating a trim control of the off-chip resistor and/or a trim control of the on-chip resistor.

Abstract: The variable gain amplifier includes a forward path that provides the amplifier variable gain, and a feedback path. The feedback path uses a switch that is turned on at low gain levels. The switch taps into the feedback resistor, shunting it to signal-ground and eliminating the feedback mechanism. This ensures that the input impedance seen at the input port does not grow excessively, using part of the feedback resistor as a passive termination at low gain levels. In this way variable gain ranges in excess of 30 dB can be achieved.

Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.

Abstract: Presented herein is a system and method for a line address computer for providing line addresses in multiple contexts for interlaced to progressive conversion. A feeder fetches a first line from a top field, fetches a first line from a bottom field corresponding to the top field, after fetching the first line from the top field, and fetches a second line from the top field after fetching the first line from the bottom field. The second line from the top field is adjacent to the first line in the top field.

Abstract: Details of media encoding and decoding devices which support generic homing sequences, and methods for operating such devices are disclosed. The use of generic homing sequences may permit an embodiment of the disclosed invention to support real-time, bit-exact testing of existing and future media encoding and decoding devices. An embodiment of the present invention may permit the initialization of encoding and decoding algorithms to a known state, enabling bit-exact testing of a large group of devices using these algorithms, including those whose specifications do not support such functionality. This capability may permit the full-speed, bit-exact, testing, of both locally and remotely situated media encoders and decoders.

Abstract: A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a first formatted input signal or a second formatted input signal to produce an amplified input signal. The data sampling module converts the amplified input signal into a first data stream in accordance with at least one first sampling clock signal when the interface is configured in the first mode and to converts the amplified input signal into a second data stream in accordance with at least a second sampling clock signal when the interface is in a second mode. The clocking module generates the first sampling clock signals from a reference clock when the multi-protocol interface is in a first operational mode and generates the second sampling clock signals based on the reference clock when the interface is in the second operational mode.

Abstract: A video processing device that generates sub-frame metadata for use in modifying a sequence of original video frames includes a video interface for receiving video data representing the sequence of original video frames, a user interface for receiving as user input sub-frame information identifying a sub-frame corresponding to a region of interest within a scene depicted in at least one frame of the sequence of original video frames and processing circuitry for generating the sub-frame metadata from the sub-frame information. Editing information associated with each sub-frame may also be included in the sub-frame metadata. Targeted sub-frame metadata can be specifically generated for use with a particular screen or screen size. A first player with a small screen and a second player with a larger screen may each receive different sub-frame metadata files, while both receive the same original video.