Abstract: A method and apparatus according to one embodiment of the invention are operable to detect the accumulation of redundant ACKs (acknowledgment signals) in a queue for streaming data packet units, and to delete a portion of the redundant ACKs to improve transmission efficiencies. In one embodiment, only the most relevant ACK is kept before the ACKs are processed for transmission. In an alternate embodiment, a ratio of defined that limits the maximum number of redundant ACKs that may be deleted. This ratio is based upon a transmission window size. The teachings of the present disclosure may also be applied to flow control in a more general sense in which a plurality of redundant signals responses are being transmitted after being aggregated.

Abstract: Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. A means for decoding LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addition). By appropriate modification of the various calculations that need to be performed when updating edge messages, the calculations may be reduced to only performing product of terms functions. When implementing such functionality in hardware within a communication device that is operable to decode LDPC coded signals, this reduction in processing complexity greatly eases the actual hardware's complexity as well. A significant savings in processing resources, memory, memory management concerns, and other performance driving parameters may be made.

Abstract: An Internet infrastructure with network nodes (access points/routers/switches) and end point devices containing encryption, decryption pipes and encryption/decryption manager analyzes encrypted packets and applies service modules when required. The network node includes processing circuitry, encryption pipe circuitry, decryption pipe circuitry, storage, an encryption/decryption manager and optionally, a proxy flow manager and a cache. The encryption/decryption manager decrypts each of the encrypted packets using the decryption pipe circuitry, to generate decrypted packets. The processing circuitry processes the decrypted packets by applying service functionality, to generate processed packets. Finally, the encryption/decryption manager encrypts the processed packets using the encryption pipe circuitry, to generate re-encrypted packets. These processed and encrypted packets are routed toward destination end point device.

Abstract: A media access controller (MAC) configurable for first and second modes of operation is provided. The MAC includes an uplink processor coupled to a plurality of uplink channels, a downlink processor coupled to a downlink, and a MAP parser coupled to the downlink processor. The downlink processor is configured to provide information to the downlink channel, including bandwidth allocation map (“MAP”) messages. Each MAP message is associated with one of the plurality of uplink channels or an uplink channel associated with one or more other MACs. The MAP parser is configured to control the MAC to receive information from a first set of one or more of the plurality of uplink channels in first mode and from a second set of one or more of the plurality of uplink channels in second mode.

Abstract: A wireless access point and multiple wireless terminals exchange utilization, status, mobility and reception characteristics. Each wireless terminal generates reception characteristics based on transmissions received from the wireless access point and from other devices in the network. In one operating mode, the characteristics gathered by the wireless devices are forwarded to the wireless access point, and, based on all received characteristics, the wireless access point selects its own transmission power for different types of the transmissions. The access point transmits to client devices at reduced power levels, however, periodic beacons and other selected non-beacon transmissions are transmitted at a high power level to facilitate association by other client devices. In another mode, all characteristics are exchanged between every wireless terminal and the access point so that each can independently or cooperatively make transmission power control decisions.

Abstract: A communication infrastructure that communicates a plurality of packets from a source device having a source address to a client device having a destination address, consisting a communication pathway with plurality of switching devices, plurality of predefined templates and associated logic and plurality of adware quarantine service functions. The source device delivers a packet containing the source address, destination address and an adware characteristic to the first of the plurality of switching devices. Then, the first of the plurality of switching devices identifies adware characteristic by comparing the packet with the plurality of predefined templates and applies the associated logic. Finally, the first of the plurality of switching devices performs selected adware quarantine service function processing that is indicated in the associated logic.

Abstract: A communication infrastructure includes an intermediate routing node that routes a plurality of packets between a source device and a plurality of destination devices, a plurality of templates stored on the intermediate routing node and a service function. The intermediate routing node, e.g., a switch, router, access point, bridge, or gateway, identifies packets containing requests for a webpage, the requests being a service attack attempt by comparing the packet with the plurality of templates. Then, the intermediate routing node denies service attack by interacting with the server and client devices. That is, the intermediate routing node sends messages with challenge mechanism to the server, based on the response or otherwise, sends messages and anti-service attack downloads to the client devices and receives response.

Abstract: An Internet infrastructure with network devices and end point devices containing service module manager and service modules, that supports packet analysis, encapsulation and vectoring, and interleaving applications. The network device that supports packet content analysis on arriving packet, consists of a plurality of packet switched interface circuitries, user interface circuitry, local storage comprising the service module manager software and a plurality of local service modules, and processing circuitry communicatively coupled to each of the packet switched interfaces, local storage and user interface circuit. The processing circuitry executes service module manager and thus analyzes the packet content and applies one or more selected local service module processing using the packet. The processing circuitry thus takes one or more actions on the packet.

Abstract: In a communication infrastructure, an intermediate node supports delivery of packets from source devices to destination devices if the source device contains no notorious content (e.g., malware or illegal content, services or distribution). The intermediate node, e.g., a switch, router, access point, bridge or gateway, contains a plurality of predefined templates and corresponding quarantine service functions. By comparing packets received with the plurality of predefined templates and associated logic, the intermediate node identifies notorious source devices such as a notorious server and notorious content. Templates target at least a portion of one or more of a domain name, IP address or URL, for example. Once identified, local and/or remote quarantine service functionality attempts to neutralize, warn, remove and/or block the notorious content at both the source and destination devices. Warnings may include human challenges to prevent malware override.

Abstract: A method of receiving information from one or more wireless uplink channels is provided. The method includes receiving information at a media access controller (MAC) from a first set of one or more wireless uplink channels in response to bandwidth allocation map (MAP) messages sent from the MAC and receiving information at the MAC from a second set of one or more wireless uplink channels in response to MAP messages sent by another MAC.

Abstract: A design methodology to debug synchronization of a signal crossing clock domains. A testable synchronization control logic utilizes a programmable register to set parameters to test signals traversing from one clock domain to another clock domain across a synchronization circuit. The register is programmed with a latency value that corresponds to a correct synchronization timing for the clock domain crossing. Other bit entries in the register provide setting of other debug parameters and indications of monitored results.

Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: An apparatus and method to use a shunt network across source terminals of cascode transistors that drive a differential current to control gain. When the gates of the cascode transistors and transistors of the shunt network are activated by a same bias voltage, the gain control is substantially independent of process, voltage and temperature variations.

Abstract: An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inbound data is detected, at which time the ADC switches to a higher power-higher precision mode to convert the data. Once data conversion is completed, the ADC switches back to the lower power-lower precision mode to conserve power.

Abstract: FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a signal stream to allow for adaptive changing of any 1 or more operational parameters that govern communications across a communication channel. FEC parameters are encoded directly into a data frame such that the data frame is treated identical to all other data frames within the signal stream. When the data frame actually includes FEC parameters, it is characterized as a CP (Control Packet) type. For example, when decoding an MPEG stream, an MPEG block that includes FEC parameters, that MPEG block is characterized as a CP MPEG block. The means by which FEC parameters are encoded and extracted from the signal stream allows for much easier adaptive modification of the manner by which signal are encoded, modulated, and processed within a communication system.

Abstract: Systems and methods are disclosed for processing data packets. Such a system may generate a header for a session and repeatedly use that header to generate packets for the session. Packets may be processed by a host processor and an associated security processor. When the security processor generates packets for the session it may prepend a header from the host processor onto packets, rather than independently generate the header.

Abstract: A high-speed bit stream data conversion circuit receives a first bit stream(s) and recovers a clock signal from the first bit stream(s). The data conversion circuit then produces a second bit stream(s) having a second lower bit rate. A control loop adjusts the phase relationship of the recovered clock signal to the first bit stream(s) to minimize data loss when the first bit stream(s) is sliced to produce the second bit stream(s). A reference clock signal produced within a clock circuit is divided to produce a reduced frequency reference clock, which is multiplexed with a test clock signal to produce an output signal. Differentially dividing the output signal produces a series of input signals for an interpolator that selectively weighs and sums the input signals as directed by the control loop to produce the recovered clock signal with the desired phase relationship relative to the first bit stream(s).

Abstract: The present invention relates to a mobile set integrating a memory efficient data storage system for the real time recording of voice conversations, data transmission and the like. The data recorder has the capacity to selectively choose the most relevant time frames of a conversation for recording, while discarding time frames that only occupy additional space in memory without holding any conversational data. The invention executes a series of logic steps on each signal including a voice activity detector step, frame comparison step, and sequential recording step. A mobile set having a modified architecture for performing the methods of the present invention is also disclosed.

Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.