Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

Abstract: A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.

Abstract: A method can allow a system to selectively control increasing of a bias source in a reference buffer or decreasing impedance looking into a output of the reference buffer for a temporary or selective time period, which can result in an increased overall efficiency of the system. The method can include at least the following steps. A first input signal is received at an input of a reference buffer. A second input signal is received from a load at an output of the reference buffer. A value of a bias source coupled to the output of the reference buffer is modulated, such that a spike of a signal at the output of the reference buffer caused by the second input signal is maintained below a threshold value. Alternatively, an impedance looking into the output of the reference buffer is modulated, such that a spike of a signal at the output of the reference buffer caused by the second input signal is maintained below a threshold value.

Abstract: A signal-generated locator for locating at least one device can include a transmitter configured to transmit at least one first signal and a receiver configured to receive at least one second signal. In addition, the signal-generated locator can have a first processing unit configured to process the at least one second signal with respect to the at least one first signal, and a display unit configured to display information processed by the processing unit, wherein the information is related to at least one device.

Abstract: A wireless network in a communication infrastructure has a packet switched backbone network and includes a plurality of access points and services at least one client device. The access points communicatively couple to the packet switched backbone network and each include access point processing circuitry and access point wireless transceiver circuitry. Each client device has client processing circuitry and client wireless transceiver circuitry. The client devices receive transmissions from other client devices serviced by the plurality of access points and characterize the received transmissions to determine signal qualities of the plurality of transmissions received from the other client devices. The client devices then report the signal qualities of the plurality of transmissions to at least one of the plurality of access points.

Abstract: A fuse corner pad is part of an integrated circuit that includes a built-in fuse contact and a plurality of auxiliary pads. The fuse contact is a conductive metallic or metalloid structure that is connected to a fuse element. The fuse contact and fuse element are used inside of the fuse corner pad for programmability (e.g., for security) and/or adjustment (e.g., trimming) of analog and/or digital signals. The fuse contact and fuse element are not required to be bonded to an external electrical connection (such as, a pin or ball). The auxiliary pads provide a variety of functional or non-functional applications, such as testing, probing, programming, and/or circuit adjustment.

Abstract: An RFIC transmitter includes a digital transmit processing module, a digital to analog converter, a filter and gain module, an up-conversion module, a power amplifier, and a transmit signal strength module. The transmit signal strength module is coupled to generate a gain adjust signal based on a measure of transmit power of an outbound RF signal, wherein the transmit signal strength module provides the gain adjust signal to at least one of the digital transmitter processing module, the digital to analog converter, the filter and gain module, the up-conversion module, and the power amplifier.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: Operating a wireless MIMO system to determine forward and reverse channel reciprocity matrices relating a first wireless MIMO device and a second wireless MIMO device of the wireless MIMO system includes, during each of a plurality of time intervals, determining a forward composite channel estimates and a reverse composite channel estimates between the first wireless MIMO device and the second wireless MIMO device to yield a plurality of forward composite channel estimates and a plurality of reverse composite channel estimates. Operation continues with creating a mathematical relationship between the plurality of forward composite channel estimates and the plurality of reverse composite channel estimates and the forward and reverse channel reciprocity matrices.

Abstract: A communication system includes a reference station and a mobile station. The reference station is operable to: receive GPS signals; generate GPS assisting data from the received GPS signals; receive SBAS signals; obtain SBAS data from the received SBAS signals; combine the GPS assisting data and the SBAS data to produce combined GPS data; and transmit the combined GPS data via a terrestrial wireless communication. The mobile station is operable to: receive the GPS signals; receive the combined GPS data via the terrestrial wireless communication; and generate positioning data from the mobile received GPS signals and the combined GPS data.

Abstract: A circuit reducing the capacitance of a switched capacitor array by mitigating switch capacitance. Reducing the effect of switch capacitance increases the frequency range of an inductor-capacitor tank containing the switched capacitor array. A pull-up circuit is coupled between a voltage source and a node. A switched capacitor and a switch are coupled to the node. The pull-up circuit biases the switch to reduce switch junction capacitance when the switch is off. In an example, a pull-up resistor is coupled between the node and a voltage source to bias the switch. In another example, a pull-up switch and pull-up resistor are coupled between the node and a voltage source to bias the switch.

Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

Abstract: A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wherein said operand store defines a plurality of lanes each holding an object, a plurality of operators associated respectively with the lanes for carrying out an operation specified in an instruction on objects in the operand lanes, a destination store for holding objects resulting from the operation on a lane by lane basis, a plurality of control stores each comprising a plurality of indicators to control for each lane whether or not an operation defined in an instruction is to be performed on that lane, and control circuitry for controlling which of said plurality of control stores is to be used to control per lane execution of an instruction, the control circuitry being operative to select a control store from the plurality of control stores based

Abstract: Methods and systems for communicating information via a plurality of different networks are disclosed herein. Aspects of the method may comprise receiving broadcast information in a mobile terminal via a VHF/UHF broadcast communication path. Cellular information in the mobile terminal comprising voice and data may be received via at least one cellular communication path. Reception in the mobile terminal may be switched between reception of the broadcast information via the VHF/UHF broadcast communication path and the cellular information via the at least one cellular communication path based on a preference indicated via the mobile terminal. The preference may be indicated via a software-controlled interface and/or a user-controlled interface. Reception in the mobile terminal may be switched between reception of the broadcast information via the VHF/UHF broadcast communication path and the cellular information via the at least one cellular communication path based on user input.

Abstract: Certain embodiments of the invention provide a method and system for symmetrically loading a divider circuit for multiband receivers. The method may comprise coupling a second divider circuit to an I component output signal of a first divider circuit and coupling a dummy load to a Q component output signal of the first divider circuit. The dummy load may comprise a load that may be equivalent to the second divider circuit. At least an I component output signal may be generated from the second divider circuit. At least a Q component signal may be generated from the second divider circuit. At least an I component signal generated from the first divider circuit may be received by the second divider circuit. At least a Q component signal generated from the first divider circuit may be received by a dummy load.

Abstract: Aspects of the invention provide a method end system for reducing signal distortion within an on-chip transceiver module. In response to receipt of a signal bearing at least one external clock frequency, at least one harmonic signal of the signal bearing the at least one external clock frequency may be generated. At least one synchronization clock frequency signal may be created from the generated at least one harmonic signal. The synchronization clock frequency signal may subsequently be supplied to at least one power source. Accordingly, the at least one power source may serve as an input power source to at least one on-chip system component of the transceiver module. In this regard, an output of the at least one power source may have at least a frequency attribute of the synchronization clock frequency signal. The synchronization clock frequency signal may reduce signal distortion produced by the at least one power source.

Abstract: An execution unit and method for performing Viterbi decoding is provided. The instruction may be built into an execution unit which executes other instructions, or in its own execution unit. In an example implementation, the instruction is used in implementing the central-office modem (ATU-C) of an asymmetric digital subscriber line (“ADSL”) system. In the example implementation, the new instruction takes as input eight input metrics and eight state metrics, and returns as output eight updated state metrics and eight decision bytes. The decision bytes contain: two ‘path’ bits to enable the previous state to be quickly identified; bits to enable the input bits to be quickly identified; and a carry bit to allow the full value of a state metric to be reconstructed, even though during the calculation only the bottom bits are calculated.

Abstract: A network device for managing data flow can have a data port configured to receive data, a plurality of pointers for pointing to the data received, and a queue for queuing the plurality of pointers. The queue can be configured to have at least one dynamic threshold therein. Furthermore, the network device can have a control module configured to adjust the at least one dynamic threshold with respect to the data flow.

Abstract: An output stage protection system for protecting NMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an embodiment, the output stage includes a pair of relatively low voltage NMOS devices coupled to a current source and IC core outputs. A first pair of relatively high voltage NMOS devices is coupled to the relatively low voltage pair and a biasing circuit. A second pair of relatively high voltage NMOS devices is coupled to a resistor, the first pair, and first and second output nodes, respectively. One or more diodes are coupled in series between the first and second output nodes and the resistor. In an embodiment, the output stage protection system protects NMOS devices in the output stage from electrostatic discharge (ESD). Input/output (I/O) pad ESD protection circuits are coupled to the I/O pads and include a clamp coupled to a local net.