Abstract: A host interface module is operable to couple the disk drive to a host device. The host interface module includes a plurality of personality modules, each of the plurality of personality modules, when coupled to the host device, is operable to accept read and write commands and transfer data to and from the host device in a corresponding one of a plurality of host interface protocols. A universal host module decodes read and write commands from the host device and transports data written to and read from the disk drive via a first of the plurality of personality modules. A multiplexer selectively couples the first of the plurality of personality modules to the universal host module in response to a selection signal. A system interface couples the universal host module to a processor and a memory of the disk controller.

Abstract: An integrated circuit (IC) assembly includes circuitry, radio frequency identification (RFID) tag circuitry, and an antenna structure. The circuitry is operable to perform at least one function. The RFID tag circuitry is coupled to process an RFID signal to produce a supply voltage for the RFID tag circuitry and to produce a response RFID signal. The response RFID signal includes information regarding at least one of: a device including the IC assembly, the IC assembly, and the at least one function. The antenna structure is coupled to receive the RFID signal and to provide the RFID signal to the RFID tag circuitry and to transmit the response RFID signal.

Abstract: An impedance transformer includes a first winding and a second winding. The first winding includes a first plurality of winding components, wherein each of the first plurality of winding components is on a corresponding layer of a first set of layers of a supporting substrate. The second winding includes a second plurality of winding components, wherein each of the second plurality of winding components is on a corresponding layer of a second set of layers of the supporting substrate and the first and second sets of layers are interleaved. The first winding has a first impedance within a desired frequency range and the second winding has a second impedance within the desired frequency range, where the first and second impedances are based on at least one of spacing, trace width, and trace length of the first and second plurality of winding components.

Abstract: Optimal synchronization mark/address mark construction. These marks can generally be referred to as sync marks. A novel means is presented by which sync marks can be generated for use within a variety of communication systems including HDD systems. The sync marks generated hereby have a largest possible minimum distance measurement that ensures highly accurate detection of the transition between the data portion and the preamble portion of information that is processed. Various types of distance measurement criteria can be employed, including a Euclidean distance measurement or a Hamming distance measurement, when selecting the sync mark from among a plurality of possible sync marks.

Abstract: Minimal hardware implementation of non-parity and parity trellis. A novel means is presented by which more than one type of trellis can be represented using a minimal amount of hardware. In magnetic recording systems and other communication systems types, there is oftentimes a need to switch between trellises which support parity and ones which do not. A very efficient means is provided with rules which will ensure joint representation of more than one trellis while requiring minimal additional hardware when compared to representing only one trellis. To represent the non-parity trellis, emanating states, resultant states, and one or more expansion states (if needed) are all that is required. Any expansion states may also need to have its path metric and path memory corresponded to one of the resultant states to ensure proper detection according to the non-parity trellis.

Abstract: A device includes a plurality of IC assemblies, where each IC assembly includes circuitry and RFID tag circuitry. The circuitry is operable to perform at least one function. The RFID tag circuitry is operable to: receive an RFID signal; process the RFID signal to produce a supply voltage for the RFID tag circuitry; interpret the RFID signal to determine whether the RFID tag circuitry is to respond to the RFID signal; and when the RFID tag circuitry is to respond to the RFID signal, transmit a response RFID signal, wherein the response RF signal includes information regarding at least one of: the device, at least one of the plurality of IC assemblies, and one or more of the at least one function.

Abstract: A method and apparatus for generating a self-correcting local oscillation includes processing that begins by generating a frequency correction signal that represents undesired tones introduced by the self-correcting local oscillation. The processing continues by generating an auxiliary frequency based on the frequency correction signal. The processing continues by compensating a synthesized frequency based the auxiliary frequency to produce a local oscillation.

Abstract: A method for an antenna architecture that handles European band cellular and broadcast channels may be provided. The method may comprise receiving at a first radio frequency integrated circuit (RFIC) integrated within a mobile terminal, first signals via a first antenna, where the first signals comprise signals within a 2100 MHz band. The method may further comprise receiving at a second RFIC integrated within the mobile terminal, second signals via the first antenna, where the second signals comprise signals within at least one of a 1800 MHz band and a 900 MHz band and receiving at a third RFIC integrated within the mobile terminal, third signals via the first antenna, where the third signals comprise signals within a VHF/UHF broadcast band.

Abstract: A method is provided for testing buffer memory. The method includes a step of testing a buffer memory having a plurality of memory locations including redundant memory locations, to determine if any of the plurality of memory locations are unusable. Next, an address of an unusable memory location of the plurality of memory locations is determined. Next, the address of the unusable memory location is stored. Next, a use of the unusable memory location is prevented based on the stored address of the unusable memory location.

Abstract: Modified branch metrics for processing bit-soft decisions to account for phase noise impact on cluster variance (CV). The present invention is able to partition a modulation scheme's constellation into two or more regions, so that the bit-soft decision branch metrics may be adjusted based on the CV of the various constellation points. A confidence level may be attached to the various constellation points based on their particular CVs. There are a number of methods to ascertain the CV of the constellation's points, including finding characteristics of various components in a communication system (transmitter, communication channel and receiver), and any method may be used within various embodiments. The modification of the branch metrics/confidence level may be performed in a communication receiver; the communication receiver may be implemented in a communication system employing the vector orthogonal frequency division multiplexing (VOFDM) portion of the broadband wireless internet forum (BWIF).

Abstract: Aspects of the invention may provide TCP offload, which may include acquiring TCP connection variables from a host and managing at least one TCP connection using the acquired TCP connection variables. At least a portion of the acquired TCP connection variables may be updated and at least some of the updated TCP connection variables may be transferred back to the host. In an aspect of the invention, the TCP connection variables may be variables that are independent of bandwidth delay product. At least a portion of the updated TCP connection variables may be utilized by the host to process the TCP connection or another TCP connection. The host may push the variables onto the stack and the TOE may pull the variables from the stack. Also, updated TCP connection variables may be pushed on the stack by the TOE and pulled from the stack by the host.

Abstract: A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host-side wireless interface, and may include additional components. The wireless network interface wirelessly communicates with the wireless user input device. The wireless user input device and the serviced host computer interact to setup the operation of the wireless user input device with the serviced host computer without requiring input from another user input device. In setting up the wireless user input device, the host-side wireless interface storing configuration information in non-volatile memory.

Abstract: The present invention provides a method of generating magnetic reference patterns on a disk or other magnetic media. This involves writing a first magnetic reference pattern to the disk with a servo writer. The disk may then be transferred to a hard disk drive. Control circuitry within the hard disk drive may recognize the first magnetic reference pattern and then position a RW head within the hard disk drive based on the first magnetic reference pattern. As the RW drive is accurately positioned based on the first magnetic reference pattern a second magnetic reference pattern may be written to the disk using the RW head. The RW head location is determined based on the velocity and phase between the read-write head and servo setter marks contained within the first magnetic reference pattern.

Abstract: A system for servicing packet data transactions and input/output transactions includes an input port, an output port, a node controller, a packet manager, and a switching module. The input port is receives communications from a communicatively coupled processing device that include packet data transactions and input/output transactions. The output port transmits communications to a communicatively coupled processing device that include packet data transactions and input/output transactions. The node controller communicatively couples to a system bus of the processing device and services input/output transactions. The packet manager communicatively couples to the system bus of the processing device and services packet data transactions. A switching module communicatively couples to the input port, the output port, the node controller, and the packet manager and services the exchange of transaction cells among the input port, the output port, the node controller, and the packet manager.

Abstract: A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and accurate reference signal is established for receiving single-ended data.

Abstract: Aspects of an encryption/decryption key generation and distribution may include generating one or more keys for use by one of a plurality of encryption/decryption devices coupled to a serial link within a chip. The generated keys may be transmitted via, for example, a high speed serial link to which one or more of the encryption/decryption devices in the chip may be coupled. The encryption/decryption devices coupled to the serial link may be adapted to examine or identify the transmitted key packets on the serial link and determine whether a particular key packet contains a key that which should be utilized by a particular one of the encryption/decryption devices. Upon identification of a key, the key may subsequently be processed and/or utilized by an integrated encryption/decryption processor associated with the encryption/decryption device to which the encryption key belongs.

Abstract: A Galois field arithmetic unit includes a Galois field multiplier section and a Galois field adder section. The Galois field multiplier section includes a plurality of Galois field multiplier arrays that perform a Galois field multiplication by multiplying, in accordance with a generating polynomial, a 1st operand and a 2nd operand. The bit size of the 1st and 2nd operands correspond to the bit size of a processor data path, where each of the Galois field multiplier arrays performs a portion of the Galois field multiplication by multiplying, in accordance with a corresponding portion of the generating polynomial, corresponding portions of the 1st and 2nd operands. The bit size of the corresponding portions of the 1st and 2nd operands corresponds to a symbol size of symbols of a coding scheme being implemented by the corresponding processor.

Abstract: A bit stream multiplexer includes an input ordering block, a plurality of multiplexers, an output ordering block, and a loop back circuitry. A bit stream demultiplexer includes an input ordering block, a plurality of demultiplexers, and an output ordering block. During testing, the transmit multiplexing integrated circuit and the receive demultiplexing integrated circuit are coupled into a circuit tester. Then, a plurality of input lines of the transmit multiplexing integrated circuit are coupled to a plurality of output data lines of the circuit tester. A loop back output of the transmit multiplexing integrated circuit is then coupled to a loop back input of the receive demultiplexing integrated circuit. A plurality of output lines of the receive demultiplexing integrated circuit are coupled to a plurality of input data lines of the circuit tester.

Abstract: An adder-subtracter circuit being adapted to process two binary input numbers in order to generate the sum or the difference of the two processed numbers depending on the state of a subtract input signal. The circuit has the capability to feed back the result of the processing to itself in order to process one input number together with the result of a previous processing instead of the second binary number.

Abstract: A “seeking” wireless terminal determines its location coordinates via access of its GPS receiver. The seeking wireless terminal then sends a seeking request via a supporting wireless network infrastructure. The seeking request includes at least one interest item entered by a user of the seeking wireless terminal and also the location coordinates of the seeking wireless terminal. The location coordinates may include an elevation of the wireless terminal. The seeking wireless terminal receives a seeking response via the supporting wireless network infrastructure that includes location coordinates of a “sought” wireless terminal. The seeking wireless terminal accesses a map segment corresponding to the location coordinates of the seeking wireless terminal and to the location coordinates of the sought wireless terminal. Then, the seeking wireless terminal displays the map segment, an icon that represents the seeking wireless terminal, and an icon that represents the sought wireless terminal.