Abstract: A method and a system for allocating memory in a memory buffer that is part of a data distribution device. Generally, the allocation of memory is for the purpose of storing datagrams. The method allocates memory in the buffer based, at least partially, on how ingress ports that are operably connected to the memory buffer have previously used the buffer to store datagrams. The system typically includes one or more detectors that monitor how various ingresses into the data distribution device are using and have used the memory buffer.

Abstract: An end-point device that is attached to a primary access point delivers a detachment logic and network address of at least a secondary access point to the primary access point. The end-point device informs the primary access point about intended detachment. The detachment logic directs the primary access point to forward data destined for the end-point device to the secondary access point after detachment in anticipation that the end-point device will be attached to the secondary access point even if detached from the primary access point. The end-point device delivers the detachment logic anytime after attachment or after detachment from the primary access point. The detachment logic directs the primary access point to store session information and network association information so that the end-point device is relieved from re-establishing communication session and re-establishing association with a data network while switching attachment from the primary access point to another access point.

Abstract: In a Power over Ethernet (POE) system, a power source equipment (PSE) device configured to deliver power to one or more powered devices (PDs) over a plurality of Ethernet transmission lines. The PSE interface includes a multi-port transmission line connector capable connecting to multiple Ethernet transmission lines, and a power source equipment (PSE) controller module integrated with the multi-port transmission line connector. The PSE controller module is capable of semi-automatic mode and legacy detection of one or more of the PDs that are coupled to the Ethernet transmission lines. The PSE controller module includes a plurality of PSE controllers corresponding to the Ethernet transmission lines, including a master PSE controller and plurality of slave PSE controllers coupled to the master PSE controller. The master PSE controller controls the slave PSE controllers, so as to provide power management to said corresponding PD devices, without an external microcontroller.

Abstract: An output stage protection system for protecting NMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an embodiment, the output stage includes a pair of relatively low voltage NMOS devices coupled to a current source and IC core outputs. A first pair of relatively high voltage NMOS devices is coupled to the relatively low voltage pair and a biasing circuit. A second pair of relatively high voltage NMOS devices is coupled to a resistor, the first pair, and first and second output nodes, respectively. One or more diodes are coupled in series between the first and second output nodes and the resistor. In an embodiment, the output stage protection system protects NMOS devices in the output stage from electrostatic discharge (ESD). Input/output (I/O) pad ESD protection circuits are coupled to the I/O pads and include a clamp coupled to a local net.

Abstract: A wireless access point and multiple wireless terminals exchange utilization, status, mobility and reception characteristics. Each wireless terminal generates reception characteristics based on transmissions received from the wireless access point and from other devices in the network. In one operating mode, the characteristics gathered by the wireless devices are forwarded to the wireless access point, and, based on all received characteristics, the wireless access point selects its own transmission power for different types of the transmission. In another mode, all characteristics are exchanged between every wireless terminal and the access point so that each can independently or cooperatively make transmission power control decisions. In a further mode, the wireless access point adjusts protocol parameters based on an assessment of the characteristics received from the client devices.

Abstract: An embedded processor system including at least one gated power unit including an internal ROM and a power controller that provides one or more gated power signals to selectively provide power to each gated power unit. The power controller provides a gated clock signal to the embedded processor to selectively control power consumption of the processor. The power controller powers down each gated power unit after freezing the processor and then powers up each gated power unit before reactivating the processor. The embedded processor system may include isolation circuitry, such as clamp circuitry or the like, that is operative to minimize current flow into each gated power unit when powered down. The gated power units may include a static function. The ROM of an embedded ROM-based microprocessor system is powered down when the microprocessor is idle to reduce or otherwise eliminate intrinsic leakage.

Abstract: A memory system is provided comprising a memory controller, a level 1 (L1) cache including L1 tag memory and L1 data memory, a level 2 (L2) cache coupled to the L1 cache, the L2 cache including L2 tag memory having a plurality of L2 tag entries and a L2 data memory having a plurality of L2 data entries. The L2 tag entries are more than the L2 data entries. In response to receiving a tag and an associated data, if L2 tag entries having corresponding L2 data entries are unavailable and if a first tag in a first L2 tag entry with an associated first data in a first L2 data entry has a more recent or duplicate value of the first data in the L1 data memory, the memory controller moves the first tag to a second L2 tag entry that does not have a corresponding L2 data entry, vacates the first L2 tag entry and the first L2 data entry and stores the received tag in the first L2 tag entry and the received data in the first L2 data entry.

Abstract: A power generating circuit includes a rectifying module and a tuning module. The rectifying module is operably coupled to convert a radio frequency (RF) signal into a voltage. The tuning module is operably coupled to tune the rectifying module in accordance with the RF signal.

Abstract: LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified to LDPC symbol-check parallel decoding or LDPC hybrid-check parallel decoding. A novel approach is presented by which the edge messages with respect to the bit nodes and the edge messages with respect to the check nodes may be updated simultaneously and in parallel to one another. Appropriately constructed executing orders direct the sequence of simultaneous operation of updating the edge messages at both nodes types (e.g., edge and check). For various types of LDPC coded signals, including parallel-block LDPC coded signals, this approach can perform decoding processing in almost half of the time as provided by previous decoding approaches.

Abstract: A filter for processing a packet can have a plurality of first masks for masking the packet, and a storage unit configured to correspond to the plurality of first masks for storing a first bit map. In addition, the filter can have a first table configured to apply the first bit map thereto. If upon applying the first bit map to the first table results in a match, then at least one specified action is implemented on the packet.

Abstract: Processing video signals may comprise converting interlaced formatted video to progressive scan video by simultaneously performing: color edge detection on a first and second field; temporal filtering on the second field and third field; and 3:2 pull down detecting on the second field and the third field. A bound output may be generated by binding an output from the color edge detecting and are output from the temporal filtering.

Abstract: Methods and systems for extending the functionality of an embedded Universal Serial Bus (USB) transceiver interface to handle threshold shift of a USB 2.0 bus during high-speed chirp are presented. A method for a transceiver of a host coupled by a USB 2.0 bus to a device includes receiving a control signal, and selecting one of a first and second zero level voltage threshold according to the control signal. The first threshold is higher than the second to compensate for a shift in a zero level of the bus during high-speed chirp. In one example, the transceiver selects the first threshold when driving a reset signal, and selects the second threshold after detecting a device high-speed chirp signal. In another example, the transceiver selects the second threshold after driving a high-speed chirp sequence. In one example, the control signal includes a signal of a host controller embedded USB transceiver interface.

Abstract: The present invention provides digital subscriber line noise mitigation techniques, and applications thereof. In an embodiment, the present invention provides a toolbox of methods and techniques for mitigating the effects of noise in xDSL systems. These methods and techniques are controllable and locatable at one or both ends of a DSL communication link (e.g., within a central office transceiver unit or a remote transceiver unit). These novel methods and techniques include: (1) per tone noise margin modification, (2) data framer constraints modification, (3) improved noise measurements; (4) more robust on-line reconfiguration processes, (5) worst case noise monitoring, (6) induced bit rate limitations, and (7) distortion noise mitigation. These methods and techniques are particularly useful for mitigating the effects of time-varying noise and impulse noise.

Abstract: A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.

Abstract: A radio frequency identification (RFID) system includes an RFID reader, an RFID tag, and a network connection module. The RFID reader includes a reader radio frequency (RF) bus transceiver. The network connection module includes a network connection RF bus transcevier, wherein the reader RF bus transceiver exchanges at least one of inbound RFID data and outbound RFID data with the network RF bus transceiver via an RF bus.

Abstract: A low power integrated circuit (IC) includes a power supply module, first circuitry, and second circuitry. The power supply module is coupled to receive a power source signal from a source external to the low power IC, derive an electromagnetic signal from the power source signal, and convert the electromagnetic signal into a supply voltage. The first circuitry is coupled to produce a first resultant from a first stimulus, wherein the first circuitry is powered via the supply voltage. The second circuitry is coupled to produce a second resultant from a second stimulus, wherein the second circuitry via powered by the supply voltage.

Abstract: A method and apparatus are provided for enabling a transmitter to have a substantially linear magnitude response and a substantially linear phase response. The transmitter includes first and second programmable gain amplifiers (PGAs). The first PGA is tuned to have a resonant frequency that is less than an operating frequency of the first PGA. The second PGA is tuned to have a resonant frequency that is greater than an operating frequency of the second PGA. A magnitude response at an output of the first PGA and a magnitude response at an output of the second PGA combine to provide a substantially linear magnitude response across a frequency range that includes the operating frequency of the first or second PGA. According to an embodiment, the first and second PGAs have the same operating frequency.

Abstract: A communication device constructed according to the present invention detects impulse noise in a preamble sequence. In detecting impulse noise in the preamble sequence the communication device first receive a preamble sequence that includes a plurality of preamble symbols. The communication device then divides the plurality of preamble symbols by at least one known preamble symbol to produce a plurality of preamble gains and/or a plurality of preamble phases corresponding to the plurality of preamble symbols. Finally, the communication device determines, based upon the plurality of preamble gains and/or the plurality of preamble phases, that at least one preamble symbol has been adversely affected by a impulse noise. The communication device may discard at least one preamble symbol that has been adversely affected by impulse noise from the plurality of preamble symbols.

Abstract: A low voltage regulated current source includes a feedback amplifier that forces a node voltage in both branches of the current mirror to equal to each other, by adjusting voltages in two branches of the current mirror to be equal to each other. The low voltage current mirror also has a higher output impedance compared to other current mirrors.

Abstract: An improved method and apparatus for Viterbi Algorithm calculations for maximum likelihood sequence estimators in communication receivers is disclosed. The calculations for the maximum likelihood sequence estimator, in accordance with the invention, utilizes a variant of the Viterbi algorithm developed by Ungerboeck in which the associated branch metric calculations for the trellis require the computation of a set of branch metric parameters. An embodiment of the present invention provides for an improved recursive method and apparatus for calculation of the branch metric parameters that reduces the number of processor clock cycles required per state metric calculation. This enables real time computation of the branch metric parameters during execution of the Viterbi Algorithm.