Abstract: Wireless local area network (WLAN) management. A novel approach is provided to associate various wireless stations (STAs) to the WLAN via appropriately selected Access Point (APs). In one implementation, a first AP services only those STAs that have functionality of a first user class (e.g., 802.11b functionality in one instance. In addition, a second AP services only those STAs that have functionality of a second user class (e.g., 802.11g functionality). The WLAN management ensures that STAs having similar characteristics (or similar functionality) are grouped together and associated with an AP that corresponds to those characteristics. For example, 802.11b STAs associate with the WLAN via an 802.11b AP. Analogously, 802.11g STAs associate with the WLAN via an 802.11g AP. When an 802.11g STA is unable to associate with the WLAN via an 802.11g AP, the STA may shift down its functionality set to 802.11b to successfully associate with the WLAN.

Abstract: Multi-component data is managed. Pixel image data is stored in a machine readable memory device. The pixel image data is decomposed into multiple colorspace components. The multiple colorspace components are stored in one continuous machine-readable memory segment of a machine-readable memory. The machine-readable memory has one or more burst boundaries.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically.

Abstract: A system for reducing the complexity of an adaptive decision feedback equalizer, for use in connection with a dual-mode QAM/VSB receiver system is disclosed. QAM and VSB symbols, which are expressed in two's compliment notation, include an extra bit required to compensate for a fixed offset term introduced by the two's compliment numbering system. A decision feedback equalizer includes a decision feedback filter section which operates on symbolic decisions represented by a wordlength which excludes the added bit representing the offset. The vestigal word is convolved with the decision feedback filter's coefficients, while a DC component, corresponding to the excluded bit, is convolved with the same coefficient values in a correction filter. The two values are summed to provide an ISI compensation signal at the input of a decision device such as a slicer. A DC component representing a pilot tone in VSB transmission systems also introduces a DC component, and additional bits, to a VSB wordlength.

Abstract: A wireless receiver includes a local oscillator, a mixer, a band pass filter, a DC offset determination module, a DC offset correction module, a subtraction module, and a down converter. The local oscillator produces a local oscillation that a mixer uses to down convert the RF information signal to produce a Very Low Intermediate Frequency (VLIF) information signal at a VLIF and having a DC offset. The band pass filter band pass filters the VLIF information signal. The DC offset determination module produces a DC offset indication for the VLIF information signal. The DC offset correction module generates a DC offset correction based upon the DC offset indication. The subtraction module subtracts the DC offset correction from the VLIF information signal to substantially remove a DC offset of the post-filtered VLIF information signal. The down converter down converts the VLIF information signal to a baseband information signal.

Abstract: A portion of a test head utilized to perform simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates. The portion of the test head includes connection sections that couple an external testing system to the portion of the test head, a restricted section positioned between said connection sections, a device interface board (DIB) having a device under test (DUT) holding section that secures the devices, said DIB positioned below said restriction section and a multi-layered rider board coupled to the devices via a coupling section, said rider board forming signal paths to route testing signals between at least the devices and the external testing system.

Abstract: An integrated digital BTSC encoder substantially implemented on a single CMOS integrated circuit is described. By saturating and adding offsets to the value of the feedback control signal in regions of operation where the calculation for the control signal is dominated by noise, an integrated circuit selectively adjusts the control signal for the spectral or wideband feedback loop, as required, so that the performance of a very low noise digital BTSC encoder complies with the requirements of the BTSC standard.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: A system for encrypting and decrypting data formed of a number of bytes using the ARCFOUR encryption algorithm is disclosed. The system includes a system bus and an encryption accelerator arranged to execute the encryption algorithm coupled to the system bus. A system memory coupled to the system bus arranged to store a secret key array associated with the data and a central processing unit coupled to the system bus wherein encryption accelerator uses substantially no central processing unit resources to execute the encryption algorithm.

Abstract: A Wireless Local Area Network (WLAN) system in which wireless terminals each operate upon battery power. One of the wireless terminals acts as a Master to coordinate the transmission and receptions of the Slaves so as to reduce the power consumed by all of the devices. The Slaves operate according to a power up and power down sequence to conserve battery power. Further, the terminals may alternate between being Slaves and being the Master to equalize battery consumption of the wireless terminals.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device. The WLAN transceiving integrated circuit includes a WLAN interface, an input buffer, a transcoder, and a processor. The WLAN interface wirelessly communicates with the at least one WLAN device to receive packetized audio data from the at least one WLAN device. The input buffer operably couples to the WLAN interface and receives the packetized audio data from the WLAN interface. The transcoder operably couples to the input buffer and receives the packetized audio data from the input buffer. The transcoder converts the packetized audio data to Pulse Code Modulated (PCM) audio data and outputs the PCM audio data to a coupled audio COder/DECoder (CODEC). The processor operably couples to the WLAN interface, the input buffer, and the transcoder.

Abstract: A network component for processing a packet can include at least one first storage unit configured to store a packet field value within the packet, at least one second storage unit configured to store at least one set of a plurality of range values, and an action implementation unit configured to implement at least one action when the packet field value is within the plurality of range values.

Abstract: An antenna includes a substantially planer substrate and a helical winding. The substantially planer substrate includes a first surface and a second surface. The helical winding includes a first pattern, a second pattern, and a plurality of interconnections. The first pattern is affixed to the first surface and the second pattern is affixed to the second surface. Connection nodes of the first pattern are coupled to associated connection nodes of the second pattern by the plurality of interconnections.

Abstract: In a DOCSIS-based communications system, different upstream channel descriptors (UCDs) all identify a single logical upsteam channel identifier (UCID) regardless of the type of cable modem (CM) to which the UCDs are sent. Different CMs having different capabilities (e.g., CMs configured according to the different DOCSIS standards 1.x, 2.0, and 3.0) receive their respective UCDs from an upstream headend. All the UCDs, however, refer to the same logical upstream channel. The different CMs therefore share this single logical upstream channel.

Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. For data-only switches (i.e. non-PoE), a midspan device is connected between the data-only switch and the PD devices so as to inject the DC power for the PD devices. The midspan device includes a combination data and management port that communicates both high speed data packets and management packets with the data-only switch. The combination data/management port obviates the need for a dedicated management port on both the midspan and the data-only switch. This eliminates the need to use an extra port on the data switch thus making better port utilization at the data switch as well as lowing the cost of the midspan.

Abstract: A transmitter includes a conversion module, a modulation parameter module, first and second up-conversion modules, a combining module, and a power amplifier circuit. The conversion module is coupled to convert a wireless protocol formatted signal into a normalized in-phase (I) symbol and a normalized quadrature (Q) symbol. The modulation parameter module is coupled to generate offset information and transmit property information. The up-conversion modules are coupled to generate up-conversion signals based on the normalized I symbol, the normalized Q symbol an in-phase local oscillation, and the offset information. The combining module is coupled to combine the up-conversion signals to produce a radio frequency (RF) signal. The power amplifier circuit is coupled to transmit the RF signal based on the transmit property information to produce a modulated RF signal.

Abstract: In Gigibit Ethernet Systems, the Trusted Platform Module (TPM) is designed to provide trust and security to a platform through integrity measurement, protected storage, and other cryptographic functions. The present invention relates to a TPM-LAN chip with separate TPM and LAN power management. The TPM-LAN chip is designed such a way that power is reduced significantly in different power management modes compared to the legacy devices. This is accomplished by turning off certain clocks during certain operating modes.

Abstract: A programmable hybrid transmitter includes a baseband processing module, an up-conversion module, and a power amplifier circuit. The baseband processing module is coupled to convert outbound data into a complex signal when the programmable hybrid transmitter is in a first mode and to convert the outbound data into a normalized complex signal, offset information, and/or transmit property information when the programmable hybrid transmitter is in a second mode. The up-conversion module is coupled to mix the complex signal with a local oscillation to produce an up-converted signal when the programmable hybrid transmitter is in the first mode and to mix the normalized complex signal with the local oscillation based on the offset information to produce a normalized up-converted signal when the programmable hybrid transmitter is in the second mode.

Abstract: A hybrid transmitter includes first and second up-conversion modules, a combining module, and a power amplifier circuit. The first up-conversion module is operably coupled to generate a first up-conversion signal based on a normalized in-phase (I) symbol, an in-phase local oscillation, and phase or frequency information. The second up-conversion module is operably coupled to generate a second up-conversion signal based on a normalized quadrature (Q) symbol, a quadrature local oscillation, and the phase or frequency information. The combining module is operably coupled to combine the first and second up-conversion signals to produce a radio frequency (RF) signal. The power amplifier circuit is operably coupled to adjust amplitude of the RF signal based on amplitude information to produce an amplitude and phase modulated RF signal.

Abstract: A planer antenna includes first and second planer helical antennas and a ground pattern. The first planer helical antenna has a first axial orientation and includes first and second helical conductive patterns on first and second surfaces of a supporting substrate. The second planer helical antenna has a second axial orientation and includes the first and second helical conductive patterns on the first and second surfaces of the supporting substrate. The ground pattern is on the second surface of the supporting substrate and provides a ground connection for the first and second planer helical antennas. The ground pattern is approximately centered at an intersection of the first and second axial orientations and the first and second planer helical antennas are off-center of the intersection of the first and second axial orientations.