Abstract: A wireless access point and multiple wireless terminals exchange utilization, status, mobility and reception characteristics. Each wireless terminal generates reception characteristics based on transmissions received from the wireless access point and from other devices in the network. In one operating mode, the characteristics gathered by the wireless devices are forwarded to the wireless access point, and, based on all received characteristics, the wireless access point selects its own transmission power for different types of the transmission. In another mode, all characteristics are exchanged between every wireless terminal and the access point so that each can independently or cooperatively make transmission power control decisions. In a further mode, the wireless access point adjusts protocol parameters based on an assessment of the characteristics received from the client devices, to detect an event such as a hidden terminal condition.

Abstract: A wireless access point and multiple wireless terminals exchange point-to-point transmission power control parameters. The wireless access point gathers parameters based on transmissions received from each of the wireless terminals. Each wireless terminal gathers parameters based on transmissions received from each of the other wireless terminals and from the wireless access point. In one operating mode, the parameters gathered by the wireless devices are forwarded to the wireless access point, and, based on all received and local parameters, the wireless access point adjusts its own transmission power and sends control signals to the wireless terminals directing transmission power adjustment. In another mode, all parameters are exchanged between every wireless terminal and the access point so that each can independently or cooperatively make transmission power control decisions.

Abstract: An RF transceiver front-end includes receiver and transmitter front-ends. The receiver front-end includes 1st and 2nd antennas, a ninety degree phase shift module and an LNA module. The 1st and 2nd antennas receive inbound RF signals and provide a first directional circular polarization. The ninety degree phase shift module phase shifts the RF signals received by the 2nd antenna. The LNA module amplifies the RF signals received by the 1st antenna and the shifted RF signals. The transmitter front-end includes a PA module and 3rd and 4th antennas, which provide a second directional circular polarization. The PA module amplifies outbound RF signals to produce amplified outbound RF signals and amplified orthogonal outbound RF signals. The 3rd antenna transmits the amplified outbound RF signals and the 4th antenna transmits the amplified orthogonal outbound RF signals.

Abstract: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A novel apparatus and a novel method are presented by which multiple Galois field computations are performed in parallel thereby speeding up the decoding processing and enhancing performance. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be perform to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact.

Abstract: Symbol by symbol MAP detection for signals corrupted by colored and/or signal dependent noise. A novel means is presented for recursive calculation of forward metrics (?), backward metrics (?), and corresponding soft information (e.g., which can be provided as LLRs (log likelihood ratios)) within communication systems in which a trellis can be employed to perform demodulation of a received signal sequence. For signals that have been corrupted by colored and/or signal dependent noise, this means provides for the ability to perform novel soft information calculation for subsequent use in iterative decoding processing. Many types of communication channels can benefit from this novel means of detection including communication channels within hard disk drives (HDDs).

Abstract: A wireless access point and multiple wireless terminals exchange utilization, status, mobility and reception characteristics. Each wireless terminal generates reception characteristics based on transmissions received from the wireless access point and from other devices in the network. In one operating mode, the characteristics gathered by the wireless devices are forwarded to the wireless access point, and, based on all received characteristics, the wireless access point selects its own transmission power for different types of the transmission. In another mode, all characteristics are exchanged between every wireless terminal and the access point so that each can independently or cooperatively make transmission power control decisions. In a further mode, the wireless access point adjusts protocol parameters based on an assessment of the characteristics received from the client devices, to detect an event such as a hidden terminal condition.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be located in any position of the unformatted block. The block encoder inserts data characters into a first set of slots of the encoded data block. The block encoder encodes K characters to produce corresponding encoded K characters. Each encoded K character includes a link field, a position field and a recoded value field. The encoded K characters are inserted into a second set of slots of the encoded data block. A synchronization header is attached to the encoded data block to distinguish control blocks from pure data blocks. The header and encoded data block are subsequently scrambled in preparation for transmission.

Abstract: A system and method that scales interlaced video fields with different sizes in a deinterlacer. The deinterlacer may expect video fields of a certain size. The input to the system may be a video stream of interlaced content, with fields having different sizes depending on the video content. The method scales the input video fields to the appropriate size expected by the deinterlacer. The expected size of the fields may be programmable. The method may provide an output with the expected size of black pixels in the absence of an input to the system.

Abstract: Methods and apparatus are provided for using explicit initialization vectors in both encryption and decryption processing. In one example, a sender generates an initialization vector, identifies cryptographic keys, encrypts data using the initialization vectors and the cryptographic keys, and transmits the encrypted data in a packet along with the initialization vector. A receiver identifies cryptographic keys, extracts the initialization vector from the received packet, and decrypts the encrypted data using the cryptographic keys and the initialization vector extracted from the received packet.

Abstract: A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.

Abstract: A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.

Abstract: A chip comprises and operational section and an input/output section. The operational section includes a controller. The input/output (I/O) section is coupled to the operational section. The I/O section comprises a transformer and a switching device. The transformer includes a primary side connected to first and second I/O ports and a secondary side connected to the operational section. The switching device is coupled to the controller and between the first and second I/O ports and a bias port, such that, under control of the controller, the switching device connects one of the first and second I/O ports to the bias port.

Abstract: A cable modem system and method are provided for using a data compression dictionary to transmit compressed payload data in a DOCSIS network while utilizing conventional cable modem termination system (CMTS) equipment. A cable modem system in accordance with the invention includes a cable modem and a CMTS adapted to send and receive compressed payload data. In one example, the cable modem is adapted to compress PDU payload data using a data compression dictionary and the CMTS is adapted to reconstruct the compressed PDU payload data that is received from the cable modem.

Abstract: A process of filtering packet data in a network device is disclosed. A descriptor table is accessed to obtain a first descriptor and a first field is extracted from a packet based on the first descriptor. An action table is accessed based on a value of the first field of the packet. Then an action from the action table is executed when a valid bit from the action table for the action is set or an action from a miss action table is executed when a valid bit from the action table for the action is not set.

Abstract: A low-noise transmitter architecture and method for high linearity, high output-swing systems such as Asymmetrical Digital Subscriber Line (ADSL) systems. The transmitter uses a switched-current DAC having a current source coupled to ground, followed by a resistive transimpedance amplifier (TIA). The resistance of the current source is typically large enough so that noise from an op-amp included in the TIA is not significantly amplified at the output. The current source may be passive and may include at least one resistor connected to ground. With a passive current source, portions of a signal output by the DAC enter either the current source or the resistive transimpedance amplifier, but not both, eliminating noise in the system produced by the current source.

Abstract: A board has connectors for interfacing to external devices mounted at a rearward edge of the board, minimizing the need to make connections and route connecting cables in the space between the board and adjacent boards installed in a computer system. In one embodiment the board is a RAID controller board and comprises a first edge portion configured to mate with a housing of a computing device, a second edge portion adjacent to the first edge portion and having an edge connector to interface the board with a corresponding slot in a computing device, at least one connector mounted proximate to a third edge portion located opposite the first edge and adapted to provide a data transfer connection with at least one compatible storage device, and a control circuit connected to the edge connector and at least one connector on the board to control the operation of the storage device.

Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.

Abstract: A scheme for sharing antenna control pins in a wireless communications device implemented on a single CMOS integrated circuit is described. By providing a routing circuit for coupling the antenna control signal to the appropriate transceiver circuitry in a multi-transceiver system, antenna control signals may be efficiently processed using a minimum of pins on the wireless communication device.

Abstract: A processor for a cable television set-top box has an interface for coupling the processor to a second processor. The processor also has a port that is coupleable to control a tuner, a demodulator and a DOCSIS module with or without DSG support. The tuner has an output coupled to the demodulator input, and the demodulator has an output to the DOCSIS module input. The demodulator's output is also coupled to a conditional access module controlled by the second processor. The processor issues commands via the port to control at least one of the tuner and the demodulator based on instructions received via the interface from the second processor.