Abstract: Data packets transmitted over a wireless network are suppressed by hardware at the transmitting end and expanded on the receiving end. This conserves bandwidth as well as reduces the processing resource requirements in both the subscriber station and the base station. An extended header element is added to a data packet that is to be transmitted over the wireless network. The extended header element contains an index that is used along with an identifier to access a rule. The rule is used to determine which bytes are to be suppressed at the transmitter and expanded at the receiver.

Abstract: A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.

Abstract: A level translator for translating a digital signal from a first voltage level to another voltage level having a higher voltage assigned to the high state of the signal comprises a latch and a pair of N-MOS transistors being coupled to the latch. This design is improved in that the N-MOS transistors are native thick oxide N-MOS transistors, each having a thin oxide layer N-MOS transistor coupled to native thick oxide transistors for reducing leakage current and improving speed in the transient state.

Abstract: A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.

Abstract: A multi-bit write pointer that is associated with a first clock can be converted to a single-bit write pointer. A multi-bit read pointer that is associated with a second clock can be converted to a single-bit read pointer. The first clock and the second clock are not synchronized. One or more guard bits can be associated with the single-bit write pointer and/or the single-bit read pointer. The single-bit write pointer and the single-bit read pointer can be compared. According to an embodiment, an error can be detected in response to comparing the single-bit write pointer and the single-bit read pointer.

Abstract: Data encoding system and method for implementing robust non-volatile memories. A data bit is stored using two memory cells. The data bit is represented by setting a voltage level of a first memory cell to a first voltage level and setting a voltage level of a second memory cell to a second voltage level. In one embodiment, the first voltage level and the second voltage level are of opposite polarity. In one embodiment, to store a data bit having the value “0,” the first memory cell is set to a first voltage level and the second memory cell is set to a second voltage level of opposite polarity to the first voltage level, and to store a data bit having the value “1,” the first memory cell is set to a third voltage level and the second memory cell is set to a fourth voltage level of opposite polarity to the third voltage level.

Abstract: A method for identifying and modeling nonlinearities in communications channels, particularly optical communication channels. A channel in general is modeled as a summation of linear and non linear terms having memory. The terms are functions of the input to the channel with respect to time, such as a sequence of input bits to the channel. In one embodiment the most recent input bits are used to access a value in a look up table. The value accessed is compared to an actual value received from the channel. The difference between the value in the table and the actual channel value may be used to correct the value in the table. When the look up table and the channel converge the look up table contains a model of the channel with memory that can model nonlinearities. A nonlinear channel having memory may also be modeled in terms of Volterra Kernels.

Abstract: Certain embodiments of the invention may be found in a method and system for a vestigial side band (VSB), quadrature amplitude modulation (QAM), NTSC, out-of-band (OOB) receiver that is integrated in a single chip. The single chip integrated digital television (DTV) receiver provides plug and play DTV receiver capability for handling both North American digital cable television and digital terrestrial broadcast television compatible systems. The integrated DTV receiver may receive all standard-definition and high-definition digital formats (SDTV/HDTV) and an on-chip NTSC demodulator handles NTSC video. An output of the NTSC demodulator may be directed to an external broadcast television system committee (BTSC) or Zweiton M decoder, or it may be sent to an on-chip audio BTSC compliant decoder. The single chip integrated DTV receiver may also comprise an integrated out-of-band QPSK receiver, which may be adapted to, for example, handle a CableCard compliant with the CableCard Specification.

Abstract: The present invention relates to a system and method for generating a blanking period indicator signal from sync information in video timing. The invention comprises an auto polarity detect processor adapted to automatically detect the polarity of at least one sync signal and a generation processor adapted to generate a DE signal.

Abstract: The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously, and a method of making the multi-port register file memory. The storage elements are arranged in N rows and M columns and store data, each column having at least one output channel or circuit. Two read port pairs are coupled to each of the storage elements and a plurality of differential sensing devices or circuits. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and at least one of the sensing device. The method of forming the multi-port register file memory comprises determining the number of storage elements and arranging the storage elements in the N rows and M columns, each column having an output channel.

Abstract: A communications network switch includes a plurality of network ports for transmitting and receiving packets to and from network nodes via network links, each of the packets having a destination address and a source address, the switch being operative to communicate with at least one trunking network device via at least one trunk formed by a plurality of aggregated network links. The communications network switch provides a method and apparatus for balancing the loading of aggregated network links of the trunk, thereby increasing the data transmission rate through the trunk.

Abstract: A system for spur cancellation comprises an input, an output, a memory, and a summer. A value corresponding to an energy level of a spur is stored in the memory. The summer is configured to receive an input signal from the input, to receive the value from the memory, to subtract the value from the input signal, and to convey an output signal to the output. The output signal is a difference of the value subtracted from the input signal.

Abstract: A Radio Frequency (RF) transceiver Integrated Circuit (IC) includes a plurality -of RF transceivers, local oscillation generation circuitry that produces a local oscillation, and local oscillation distribution circuitry. The local oscillation distribution circuitry couples to the local oscillation generation circuitry and includes a plurality of local oscillation repeater circuits. Each local oscillation repeater circuit corresponds to a respective one of the plurality of RF transceivers (transmitter, receiver, or both) Each local oscillation repeater circuit includes a local oscillation repeater circuit input, a local oscillation repeater circuit interface driver output coupled to respective one of the plurality of RF transceivers, and a local oscillation repeater circuit output.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A balancing/unbalancing (balun) structure for operating at frequency f1 includes a microstrip printed circuit board (PCB). A balun on the PCB includes two input ports are coupled to a differential signal. An isolated port is connected to ground through a matched resistance. An output port is coupled to a single-ended signal corresponding to the differential signal. A plurality of traces on the PCB connect the two input ports, the load connection port and a tap point to the output port. A f2 rejection filter on the PCB is wrapped around the balun and includes a first folded element with a transmission length of ?2/4 and connected to the output port. A second folded element has a transmission length of ?2/4 and connected to the tap point. A third folded element connects the tap point to the output port and has a transmission length of ?2/4.

Abstract: A near field RFID system includes an RFID reader and an RFID tag. The RFID reader includes a transmit path and a receive path, wherein the transmit path includes: an encoding section coupled to convert data into encoded data; a digital to analog conversion module coupled to convert the encoded data into an analog encoded signal; a power amplifier coupled to amplify the analog encoded signal; and a plurality of coils coupled to generate a plurality of electromagnetic fields from the analog encoded signal. The RFID tag that includes: a coil coupled to generate a current and a recovered signal from at least one of the plurality of electromagnetic fields; a power recovery circuit coupled to generate a voltage from the current; and a data processing section coupled to process the recovered signal, wherein the data processing section is powered via the voltage.

Abstract: In a computing management system authentication procedures are secured by protecting keys and/or processes used during the authentication procedures. In some embodiments the system cryptographically protects any keys used to mutually authenticate a management console and client. In some embodiments the system cryptographically protects execution of one or more of the algorithms used to mutually authenticate a management console and client.

Abstract: A supervisory communications node monitors and controls communications with a plurality of remote devices throughout a widely distributed network. A method is provided to convey and maintain information used to synchronize the packetization and burst operations within the network. During session setup, jitter constraints indirectly are used to explicitly communicate a synchronization timing reference. The timing reference is set at the beginning of a phase/period boundary used to service the session. In an embodiment, the announcement of the first grant is used as an explicit indication of the synchronization timing reference value. In another embodiment, the synchronization timing reference value is inferred if a remote device receives contiguous voice grants meeting certain conditions. In an embodiment implementing periodic scheduling, the actual arrival of the first grant is used to infer the synchronization timing reference value.

Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required.

Abstract: Methods and apparatuses for compensating for differences in communication system transmit and receive clock signal frequencies include buffer timing modification and sample addition. In buffer timing modification, a buffer clock signal is interrupted as needed to slow the rate of data through the buffer. In sample addition, pseudo samples are inserted into a data stream to compensate for timing differences.