Abstract: Optimal Decision Feedback Equalizer (DFE) coefficients are determined from a channel estimate by casting the DFE coefficient problem as a standard recursive least squares (RLS) problem and solving the RLS problem. In one embodiment, a fast recursive method, e.g., fast transversal filter (FTF) technique, is used to compute the Kalman gain of the RLS problem, which is then directly used to compute MIMO Feed Forward Equalizer (FFE) coefficients. The FBE coefficients are computed by convolving the FFE coefficients with the channel impulse response. Complexity of a conventional FTF algorithm may be reduced to one third of its original complexity by selecting a DFE delay to force the FTF algorithm to use a lower triangular matrix. The length of the DFE may be selected to minimize the tap energy in the FBE coefficients or to ensure that the tap energy in the FBE coefficients meets a threshold.

Abstract: A system for adding a time stamp to transmission traffic on a wireless network comprises a front end processor that receives a packet from the network and generates a Start Of Frame pulse and a LENGTH field corresponding to a length of the packet. A time stamp generator generates a time stamp by sampling the system master time counter. A synchronizer receives the SOF pulse and the LENGTH field from the front end processor, and generates a control signal. A multiplexer inputs the packet from the front end processor, the control signal and the time stamp, and outputs a modified packet with a field in the packet replaced by the time stamp.

Abstract: A power-down biasing circuit includes a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first pre-chargeable capacitor is connected between the gate of the first NMOS transistor and ground. A plurality of NMOS transistors form a current multiplier and have gates connected to the current reference. A plurality of current mirrors are connected to drains of the plurality of NMOS transistors and to output switches.

Abstract: A voltage regulator includes a first stage capable of receiving a reference voltage and capable of having a first current flowing through the first stage. A second stage is capable of having a second current flowing through the second stage. A third stage is capable of outputting an output voltage and capable of having a third current flowing through the second stage. The first, second and third currents are proportional to each other throughout a range of operation of the voltage regulator between substantially zero output current and maximum output current. The first stage drives the second stage as a low input impedance load.

Abstract: A method for increasing upstream bandwidth per cable modem user in a cable communications system that includes a cable modem termination system (CMTS) and a plurality of cable modems is provided. The method permits a cable modem to transmit data to the CMTS on multiple upstream channels simultaneously using a technique called “channel bonding.” Bandwidth allocation is achieved by transmitting from a CMTS to a cable modem a unique bandwidth allocation message for each upstream channel in a bonded group of upstream channels, wherein the combination of unique bandwidth allocation messages collectively allocates requested bandwidth across the bonded group.

Abstract: Methods and systems for synchronizing a reset signal with a local clock that drives a circuit. In the circuit, the reset signal can be used to reset one or more flip-flops, memory devices, and/or logic. Sychronization of the reset signal allows the reset signal to change at an appropriate time period in relation to the lock clock signal driving the circuit. This ensures the circuit will remain stable during reset, and no data will be lost as it is processed in the circuit. Other aspects of the invention can include using a plurality of reset signals (e.g., software, hardware, local software, etc.) to form the reset signal and using a reset control system to control resets during testing of the circuit.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A system, method, and computer program product for synchronizing time between a centralized controller device and at least one subscriber device on an Ethernet Passive Optical Network (EPON). The MAC control layer of an EPON device is expanded, and additional messaging control is added via the transmission of Ethernet frames. The expansion prevents reliance on a physical layer signal. The time synchronization also allows a time stamp to be incorporated into a message. Thus, bandwidth is not wasted by simply transmitting a time stamp by itself. In an embodiment, the centralized controller device measures the time difference between the time at which a particular ranging request is transmitted and the time at which the particular ranging request is received. The time difference represents the time adjustment value for the particular subscriber device and allows the device to synchronize its time with that of the centralized controller device.

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract: A method for synchronizing counters in a terminal device, such as a cable modem in a DOCSIS-based system, with those of an administrative device, such as a headend. A cable modem advances its frame counter. With each increment of the frame counter, the cable modem's minislot counter advances by an amount equal to the number of minislots per frame. Likewise, with each increment of the frame counter, the cable modem's timestamp counter is incremented by the number of timestamps per frame. This continues until the counters at the cable modem are within one frame of the headend's counters. The minislot counter is then incremented. With each increment of the minislot counter, the timestamp counter is incremented by an amount equal to the number of timestamps per minislot. This continues until the cable modem's counters are within a minislot of the headend's counters. The timestamp counter is then incremented until the cable modem's counters match those of the headend.

Abstract: A table searching system for facilitating high speed linear searching of a table of information by a plurality of searching agents is provided. The system includes: a memory unit for storing a table of information including a plurality of data entries each having data contents; a plurality of searching agents each being communicatively coupled with the memory unit, and having a port for receiving an associated search key value; and a memory controller unit providing a centralized interface between the memory unit and each of the agents, the controller unit being operative to control the memory unit to provide the contents of a current one of the table entries to each of the agents during each of a plurality of cycles of operation. Each of the searching agents is operative to determine an associated best matching one of the data entries based on comparisons between the associated key value and the contents of the data entries provided by the memory unit.

Abstract: A process of controlling and monitoring a wireless hotspot by a wireless service provider is disclosed. Data is received from an access point of a wireless hotspot for wireless portable devices and is translated into wireless network data having a format intelligible by a wireless service provider. The wireless network data is sent to the wireless service provider and wireless service provider data is received from the wireless service provider. The wireless service provider data is translated into access point data having a format intelligible by the access point and the access point data is forwarded to the access point.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is received. A heat spreader has a first surface and a second surface. The first heat spreader surface is attached to the second substrate surface. A plurality of solder balls are attached to the second substrate surface outside an outer dimensional profile of the heat spreader. The second heat spreader surface is configured to be coupled to a printed circuit board (PCB).

Abstract: The network device includes a transceiver, a pattern generation unit and a pattern recognition unit. The transceiver connects to a communications medium. The pattern generation unit connects to the transceiver. The pattern generation unit is configured to generate a first code word in response to a self-test signal. The pattern recognition unit connects to the communications medium and a network entity. The pattern recognition unit is configured to receive the first code word from the transceiver and to determine whether the first code word includes a loop back pattern. The pattern recognition unit is configured to generate a second code based upon the first code word and to include in the second code word a pattern different from the first code word.

Abstract: A wireless interface device services communications between a wirelessly enabled host and at least one user input device. The wireless interface device includes a wireless interface unit, a processing unit, an input/output unit, and a power management unit. The wireless interface unit wirelessly interfaces with the wirelessly enabled host using a communication interface protocol. The power management unit operably couples to the wireless interface unit, the processing unit, and the input/output unit. The wireless interface unit supports paging operations in which the wireless interface device is able to receive a page during a wirelessly enabled host in a page scanning period that corresponds to a duration of the page hopping sequence of the host.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is received. A heat spreader has a first surface and a second surface. The first heat spreader surface is attached to the second substrate surface. A plurality of solder balls are attached to the second substrate surface outside an outer dimensional profile of the heat spreader. The second heat spreader surface is configured to be coupled to a printed circuit board (PCB).

Abstract: A multi-stage amplifier assembly configured to receive a terrestrial digital television (“DTV”) input signal including multiple frequency channels. The amplifier assembly optionally includes a PIN diode coupled across differential inputs to a first stage of the multi-stage amplifier assembly. The PIN diode is controlled to attenuate the input when an exceptionally large signal is present in a channel adjacent to a desired channel. The PIN diode, essentially a variable resistor, permits the multi-stage amplifier assembly to maintain dynamic range in such situations for reasonable tradeoffs. The amplifier assembly further optionally includes an out-of-band second stage LNA. The amplifier assembly further optionally includes a multi-band input filter. The multi-band filer insures that the AGC operates on the TV band of interest, thus improving the linearity of the system. The invention can be implemented in CMOS and/or SiGe.

Abstract: A differential amplifier is configured in a cascode configuration that includes input transistors that are connected to corresponding cascode transistors. The gates of the cascode transistors are tied together to form a common bias for the cascode devices. The input transistors of the differential amplifier receive a differential input signal that is amplified and outputted to an output circuit that is connected to the cascode transistors. The cascode devices require a bias voltage for proper operation. Preferably, the bias voltage puts the cascode devices into the saturation region. The gates of cascode devices are coupled together and connected to a bias terminal. In embodiments of the invention, the bias terminal is connected to another terminal of the chip to provide the bias for the cascode devices.

Abstract: A low-speed delay locked loop (DLL) facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.