Abstract: Training signals can be chosen based on stored prior connection information to reduce the use of extra tones in transmitted training signals and thereby improve receiver performance. By choosing training signals based on the stored prior connection information, it is possible to make the training signals indirectly a function of the loop impairments. One advantage of this scheme is that we can choose to omit certain tones in the training signals, based on previous connection information, on a loop-by-loop basis. For example, in an ADSL Transceiver Unit-Central office end (ATU-C) device, per-local-loop prior connection information may be employed to select DMT tones to be included in downstream training signals. Similarly, in an ADSL Transceiver Unit-Remote terminal end (ATU-R) device, prior connection information may be employed to select DMT tones to be included in upstream training signals.

Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. The PSE controller includes a resistorless switch to measure the current. The resistorless switch includes a sense transistor and a current mirror to allowing the PSE controller to calculate the current based upon a replica current.

Abstract: A method for reducing a propagation delay of a digital filter. The digital filter has an input path and an output path and includes a set of delay elements and a number of taps. The taps couples the input path to the output path. Each of the taps includes a coefficient, a multiplier and an adder. Each of the delay elements is disposed between two adjacent taps. The delay elements are placed in both the input path and the output path of the digital filter, such that the digital filter has fewer delay elements in the input path than a direct-form digital filter having the same number of taps in a direct-form structure and has fewer delay elements in the output path than a transposed-form digital filter having the same number of taps in a transposed-form structure, and such that the digital filter has same transfer function as the direct-form digital filter and the transposed-form digital filter.

Abstract: A system and method for restricting access to a wireless network is disclosed herein. One or more access points are generally associated with the wireless network (e.g., an IEEE 802.11 wireless network), and a visitor gateway for automatically preventing visiting user from directly entering the wireless network. A command and control center communicates with the access points and the visitor gateway and controls data transfer and routing thereof. The visitor gateway can communicate with a remote computer network (e.g., the Internet) and restricts access to the wireless network by a visiting user through or from the remote computer network. The command and control center also can automatically route the visiting user to the visitor gateway when the visiting user attempts to access an access point associated with the wireless network.

Abstract: A system and method for creating run time executables in a configurable processing element array is disclosed. This system and method includes the step of partitioning a processing element array into a number of defined sets of hardware accelerators, which in one embodiment are processing elements called “bins”. The system and method then involves decomposing a program description in object code form into a plurality of “kernel sections”, where the kernel sections are defined as those sections of object code which are candidates for hardware acceleration. Next, mapping the identified kernel sections into a number of hardware dependent designs is performed. Finally, a matrix of the bins and the designs is formed for use by the run time system.

Abstract: A slicer with large input common mode range is provided. The slicer includes an input stage coupled to receive an input signal, a current source for providing current for the input stage, a self-biased load coupled to the input stage to provide an initial output signal, and an inverter for inverting the initial output signal to provide a final output signal. The input stage includes a first circuit including a plurality of transistors and a complimentary circuit including a plurality of transistors. When a low common mode input voltage causes the transistors of the first circuit to turn off, the transistors of the complimentary circuit will take over to accomplish the same task as the first circuit.

Abstract: The radio frequency integrated circuit (RFIC) electrostatic discharge (ESD) circuit includes an integrated circuit pin and a radio frequency (RF) ESD circuit. The integrated circuit pin provides coupling to an antenna. The RF ESD circuit is operably coupled to the integrated circuit pin, wherein the RF ESD circuit provides ESD protection at the integrated circuit pin, provides coupling of inbound RF signals from the antenna to low noise amplifier, and provides coupling of outbound RF signals from a power amplifier to the antenna.

Abstract: Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of the present invention attempt to maintain the proper current ratio between reference and output supplies by adjusting the reference output of the current mirror. An existing reference voltage on the output side of the mirror can be used or a reference voltage can be created to be used for the voltage regulation of the reference side of the current mirror.

Abstract: A circuit for protection of a transceiver input includes an input transistor and a first resistor connected between the drain of the input transistor and an input node. A plurality of reverse-biased diodes connected between a supply voltage and the input node. An output node is connected to the source of the input transistor. A first forward-biased diode connected between the power supply and the plurality of reverse-biased transistors. A second forward-biased diode and a second resistor are connected between the first forward biased transistor and the gate of the input transistor. A pre-driver circuit includes first and second transistors forming a differential pair and driven by a differential input voltage. A third transistor is connected between sources of the first and second transistors and ground. First and second resistors are connected to drains of the first and second transistors, respectively. A fourth transistor is connected between a power supply voltage and the first and second resistors.

Abstract: A “virtual on-chip memory” that provides advantages as compared to an on-chip memory that utilizes a cache. In accordance with the invention, when a CPU attempts to access a memory address that is not on-chip, the access is aborted and the abort is handled at a page level. A single page table is utilized in which each entry constitutes an address in the virtual address space that will be mapped to a page of on-chip memory. The CPU obtains the missing data, updates the page table, and continues execution from the aborted point. Because aborts are handled at the page level rather than the line level, the virtual on-chip memory is less expensive to implement than a cache. Furthermore, critical real-time applications can be stored within a non-virtual portion of the memory space to ensure that they are not stalled.

Abstract: A Power over Ethernet electrostatic discharge protection circuit has a first diode with an anode coupled to a positive power port and a cathode coupled to an ESD protection port. A second diode has an anode coupled to ground and a cathode coupled to the positive power port. A third diode has an anode coupled to a negative power port and a cathode coupled to the ESD protection port.

Abstract: A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is implemented within a larger general purpose processor for handling the streams of dependent instructions.

Abstract: A secure processor such as a trusted platform module supports multiple security functions within a single secure processing environment. For example, the secure processor may be configured to perform functions in accordance with the TPM specification and to perform other, non-TPM, security functions. These security functions may be operated independently such that the operation of one security function does not violate or compromising the security of other security functions.

Abstract: Data packets transmitted over a wireless network are suppressed by hardware at the transmitting end and expanded on the receiving end. This conserves bandwidth as well as reduces the processing resource requirements in both the subscriber station and the base station. An extended header element is added to a data packet that is to be transmitted over the wireless network. The extended header element contains an index that is used along with an identifier to access a rule. The rule is used to determine which bytes are to be suppressed at the transmitter and expanded at the receiver.

Abstract: An apparatus and method for multi-point detection in a power source equipment (PSE) device is provided. During multi-point detection, a series of at least four currents is sequentially applied to a link port of the PSE device. Each current is applied during a different measurement interval. A voltage measurement sample is obtained for each of the measurement intervals. A difference in voltage between alternating voltage samples is determined and used by a detection module to determine whether a valid power device is coupled to the link port of the PSE.

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted on a first surface of a stiffener. A first surface of a substrate is attached to a second surface of the stiffener that is opposed to the first surface of the stiffener. A bond pad of the IC die is coupled to a contact pad on the first surface of the substrate with a wire bond. The wire bond is coupled over a recessed step region in the first surface of the stiffener and through a through-pattern in the stiffener that has an edge adjacent to the recessed step region. The through-pattern in the stiffener is one of an opening through the stiffener, a recessed portion in an edge of the stiffener, or other through-pattern.

Abstract: In one embodiment, an apparatus includes a first integrated processor, a second integrated processor, and a security processor. The first integrated processor has one or more network interfaces for receiving packets and also has a second interface. The second integrated processor is coupled to the second interface. A security processor is coupled to the second integrated processor. Also, a storage switch is contemplated employing one or more line cards which include the apparatus. The storage switch further includes at least one switch fabric card coupled to the at least one line card, wherein the switch fabric card is configured to route packets from the at least one line card and from one or more storage devices on a switch fabric. In another embodiment, the integrated processors may be systems on a chip (SOCs).

Abstract: A process of filtering packet data in a network device is disclosed. At least one mask is applied to a portion of an incoming packet and a field is extracted from the portion of the incoming packet. A rules table is searched for a matching value for the extracted field and one of a hit and a miss is recorded depending on the matching value. A combination table is accessed based on the at least one mask and the one of the hit and the miss is combined with another search result to obtain a combined search result. One of a hit action and a miss action is executed from the combination table based on the combined search result.

Abstract: A small form factor USB Bluetooth dongle includes a printed circuit board (PCB), a USB contact area, and a radio frequency (RF) transceiver die. The PCB includes a first primary surface and a second primary surface. The USB contact area is fabricated on the first primary surface. The RF transceiver die is mounted on the second primary surface, wherein the RF transceiver is in accordance with Bluetooth.

Abstract: An optical line terminal (OLT) monitors and controls communications with a plurality of optical nodes (ONs), such as optical network units (ONUs) and/or optical network terminators (ONTs), within a passive optical network (PON), such as, but not exclusively, an Ethernet-based passive optical node (EPON). A tagging mechanism is implemented to identify an origin ON that introduces a frame into the PON segment linking the origin ON with the OLT. The origin ON produces a PON tag to associate its identifier (ON_ID) to the frame. The PON tag facilitates filtering and forwarding operations, and enables the physical layer interface (PHY) to the PON segment to emulate a point-to-point and/or shared communications link. The PON tag allows a MAC control layer to create virtual ports to traffic incoming and outgoing optical signals, and supply the virtual ports to a forwarding entity for frame filtering and forwarding.