Abstract: An oscillator circuit providing quadrature outputs and enabling instantaneous control over phase, frequency and amplitude of the output waveforms is disclosed. In one embodiment, the oscillator circuit comprises an oscillation loop, at least one capacitor switching circuit coupled to the oscillation loop, and a synchronization signal having an output coupled to the at least one capacitor switching circuit. The synchronization signal may be derived internally from the oscillation loop or externally from an external oscillator.

Abstract: A Space Time Transmit Diversity (STTD) Decoder includes a physical channel despreader, a delay buffer, an upper processing branch, a lower processing branch and a combiner. The upper processing branch is operable to apply a conjugate of a first channel estimate to the delay buffer symbol output and produce non STTD encoded symbols. The lower processing branch is operable to read delayed delay buffer symbol outputs and apply a conjugate of a second channel estimate when active in the STTD mode. The lower processing branch then may apply an STTD decoder scheme to the delay buffer symbol output to produce non STTD encoded symbols. The combiner then combines the non STTD encoded symbols of the upper processing branch and non STTD encoded symbols of the lower processing branch to produce a single set of non STTD encoded symbols.

Abstract: A method is provided for reducing the number of conductive interfaces required to interface to a SDRAM. One or more conductive interfaces can be used, during a cycle, to both transfer data and provide a command or an address to an SDRAM. More specifically, each of the conductive interfaces on a controller can be used to control one data conductive interface and one of an address, bank address, RAS, CAS, or WE conductive interface on an SDRAM. The interface for the present invention provides a lower conductive interface count ASIC with a smaller package than a conventional SDRAM interface.

Abstract: A power management scheme for a wireless communications device substantially implemented on a single CMOS integrated circuit is described. The present invention provides a method and apparatus for generating first and second clock signals for a wireless communication device, with the first and second clock signals corresponding first and second power levels, depending on the operating mode of the wireless communication unit. In the first operating state, the transceiver in the RF analog module is operational and the clock generator provides a first clock signal having the high-speed, high-accuracy characteristics necessary to maintain efficient operation of the transceiver. In a second operating state, the transceiver in the RF analog module is turned off. In this second operational state, the clock generator provides a second clock signal having a frequency and quality sufficient to maintain efficient operation of the digital modules in the wireless communication device.

Abstract: Optimizing a radio link is done by acquiring at least OSI layer one and two performance measurements, determining an optimum setting collection for at least OSI layer three to a top layer, then configuring at least the OSI layer three to the top layer based upon the optimum setting collection. The top layer is at least OSI layer four. The invention includes optimized radio links, methods of making optimized radio links, revenue generating making optimized radio links by providing means for optimizing the radio link.

Abstract: A system and method according to the present invention allow two or more peer-to-peer wireless devices to automatically connect to each other with no knowledge or pre-configuration of client/server roles. According to a first aspect of the present invention, a wireless device performs inquiries at a random interval, and performs an inquiry scan and a page scan when not performing the inquiries. Upon receiving a first device address in response to one of the inquiries, the wireless device performs a first page using the device address to establish a connection. And upon receiving an inquiry during the inquiry scan, the wireless device responds with a second device address, and if a second page is received during the page scan, establishes a connection.

Abstract: A resonator-synchronized oscillator for resonance mode selection is disclosed. In one embodiment, the resonator-synchronized oscillator comprises an oscillation loop, at least one capacitor switching circuit coupled to the oscillation loop, and a multi-mode resonator having an output coupled to the at least one capacitor switching circuit. The output signal of the resonator is used to synchronize the oscillator using switched capacitor structures to instantaneously reset the phase of the resonator-synchronized oscillator.

Abstract: A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.

Abstract: A radio frequency integrated circuit (RFIC) includes a die and a package. The die includes a radio frequency (RF) input/output (I/O) section, an RF to baseband conversion section, and a baseband processing section. The package includes a ball grid array and an antenna. The antenna is located on one edge of the package and the solder balls of the ball grid array proximal to the antenna are used to couple the RF I/O section of the die to the antenna.

Abstract: An HSDPA rake receiver has a plurality of rake fingers. Different channels may experience different spreading factors. The channel estimate (CE) and the CE delay may be affected and depend on the spreading factor. The CE delay is related to the individual rake finger output buffer size. According to the structure of the present invention, an adaptive channel estimate delay that depends on the spreading factor may result in improved performance.

Abstract: An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

Abstract: An integrated multimode radio includes a multimode receiver and a multimode transmitter. The multimode receiver includes a shared receiver front-end, a receiver multiplexor, and a plurality of receiver IF stages. The multimode transmitter includes a shared transmitter front-end, a transmitter multiplexor, and a plurality of transmitter IF stages.

Abstract: FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a signal stream to allow for adaptive changing of any 1 or more operational parameters that govern communications across a communication channel. FEC parameters are encoded directly into a data frame such that the data frame is treated identical to all other data frames within the signal stream. When the data frame actually includes FEC parameters, it is characterized as a CP (Control Packet) type. For example, when decoding an MPEG stream, an MPEG block that includes FEC parameters, that MPEG block is characterized as a CP MPEG block. The means by which FEC parameters are encoded and extracted from the signal stream allows for much easier adaptive modification of the manner by which signal are encoded, modulated, and processed within a communication system.

Abstract: A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB) or the communication ASIC to another communication ASIC. The high-speed bit stream interface includes a line side interface, a board side interface, and a plurality of signal conditioning circuits. The signal conditioning circuits service each of an RX path and a TX path and include a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

Abstract: A system providing support for user transactions in a media exchange network is disclosed. An embodiment of the present invention may comprise a television display, storage, and a set top box, and may provide an interface device for receiving from a user associated authorization device, information for authorizing user transactions via a communication network. A user transaction may comprise the exchange, purchase, storage, or consumption of media such as, for example, audio, still images, video, and data. The communication network may comprise, for example, a cable infrastructure, a digital subscriber line infrastructure, a wireless infrastructure, and may be the Internet. The system may provide for the completion of the user transaction without divulging the identity of the user to a vendor.

Abstract: Carrier frequency offset (CFO) estimation from preamble symbols. Any communication receiver may be adapted to perform the CFO estimation. The CFO estimation is performed using a low complexity, high accuracy CFO estimation method. The operation may be described as follows: each element of a received sequence is divided by the corresponding preamble element, the resulting sequence is divided into N subgroups, and each subgroup is then averaged. The phase differential of the resulting sequence is computed, averaged, and used to compute an estimate of the carrier frequency offset. This approach to performing CFO estimation is of relatively high estimation accuracy and of relatively low computational complexity.

Abstract: The receiver is provided which comprises a mixer, a low pass filter coupled to the mixer and a plurality of gain controllers serially coupled to an output of the low pass filter (LPF). A plurality of analog-to-digital converters (ADCs) is coupled so that an input of a first of the ADCs is coupled to the output of the LPF. An input of each of a remaining portion of the ADCs is individually coupled to a corresponding output of each of the serially coupled gain blocks. An output path traced from the output of the LPF to an output of each of the analog-to-digital converters may be referred to as a processing path. Each processing path may comprise a gain controller and an ADC, except for the first processing path, which may have an ADC coupled directly to the output of the LPF.

Abstract: A telephony bridging device operates within infrastructure that includes a packet data network (Internet) and the Public Switched Telephone Network (PSTN) telephony network and supports a coupled POTS telephony device. The telephony bridging device is operable to bridge calls between every two of the POTS telephony device, the PSTN network, and the packet data network (Internet). The telephony bridging device selectively bridges incoming calls to the POTS telephony device, to remote PSTN terminals, and to remote VoIP terminals based upon telephony bridging instructions. These telephony bridging instructions may be stored locally or remotely.

Abstract: A method to perform adaptive channel filtering on a Radio Frequency (RF) bursts in a cellular wireless communication system. This method first filters an input signal with a first stage filter having a first bandwidth to produce a first stage output signal. Then the first stage output signal is filtered with a second stage filter having a second bandwidth narrower than that of the first stage filter to produce a multi-stage output signal. A comparison between first stage performance measurements and multi-stage performance measurements determine the mode of operation of the adaptive multistage filter. A first mode of operation, selected when the first stage performance measurement compares favorably with the second stage performance measurement, selects the output of the first stage filter as the output of the multi-stage filter. Otherwise, a second mode of operation selects the output of the second stage filter as the output of the multi-stage filter.