Abstract: A high-speed CMOS transmit/receive antenna switch includes a first transistor, a second transistor and a parasitic compensation network. The first transistor is operably coupled to an antenna, to a transmit path, and to receive a transmit/receive (T/R) control signal. The second transistor is operably coupled to the antenna, the receive path, and to receive the T/R control signal. When the T/R control signal is in a first state, the first transistor is active and the second transistor is inactive such that the transmit path is coupled to the antenna. When the T/R control signal is in a second state, the second transistor is active and the first transistor is inactive such that the receive path is coupled to the antenna. The parasitic compensation network is coupled to compensate for adverse effects of parasitic components of the first and second transistors at operating frequencies of the transmit/receive antenna switch.

Abstract: Presented herein is a system and method for byte slice based DDR timing closure. In one embodiment, there is presented a method for synthesizing/laying out a dual data rate memory, said method comprising synthesizing/laying out a portion of the dual data rate memory; replicating the portion; and placing the synthesized/laid out portion and the replicated portions in proximity to a corresponding plurality of pads.

Abstract: Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Abstract: LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks. Encoded bits from multiple level LDPC codewords within each of the sub-blocks are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.

Abstract: A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to strobe in data bits and output a pair of data bits onto the internal bus each half clock cycle.

Abstract: Operating a wireless MIMO system to determine forward and reverse channel reciprocity matrices relating a first wireless MIMO device and a second wireless MIMO device of the wireless MIMO system includes, during each of a plurality of time intervals, determining a forward composite channel estimates and a reverse composite channel estimates between the first wireless MIMO device and the second wireless MIMO device to yield a plurality of forward composite channel estimates and a plurality of reverse composite channel estimates. Operation continues with creating a mathematical relationship between the plurality of forward composite channel estimates and the plurality of reverse composite channel estimates and the forward and reverse channel reciprocity matrices.

Abstract: New version packet data devices support a backwards-compatible signal format. New version devices operate within a first frequency band while old version devices operate within a second frequency band. The first frequency band differs from but overlaps with the second frequency band. The new version devices may operate on a first carrier frequency (within the first frequency band) while old version devices may operate at a second carrier frequency (within the second frequency band). The new version devices and/or the old version devices may also support carrier-less modulations. Preamble, header, and trailer portions of a new version signal include a plurality of spectral copies of a baseband modulated signal. One or more of these spectral copies of the baseband modulated signal is/are indistinguishable from corresponding components of an old version signal. The payload of the new version signal may be formed in the same manner or may be formed in have a wider bandwidth, higher data rate format.

Abstract: In an RF communication system, aspects for cellular network and intelligent integrated broadcast television downlink with intelligent service control with feedback may comprise generating a request in a mobile terminal for media to be delivered to the mobile terminal. The mobile terminal may transmit the request via a cellular service. The mobile terminal may receive the requested media having a specified quality of service via a single integrated cellular and VHF/UHF baseband processing integrated circuit. The received requested media may be received from a cellular broadcast service, the cellular service and/or a VHF/UHF broadcast service. The mobile terminal may negotiate for an acceptable quality of service with a service provider that controls delivery of the media. The media may be delivered via at least one of the cellular broadcast service, the cellular service and the VHF/UHF broadcast service.

Abstract: Methods and systems for locking a phase locked loop (PLL) are disclosed herein. A first impulse signal may be generated utilizing an input reference signal. A second impulse signal may be generated utilizing an input divided signal. A programmable delay signal may be generated based on the generated first impulse signal and the generated second impulse signal. The generation of the first impulse signal and the generation of the second impulse signal may be controlled via the generated programmable delay signal. The generated first impulse signal and the generated second impulse signal may be delayed utilizing a programmable delay. The delayed first impulse signal and the delayed second impulse signal may be ANDed to generate the programmable delay signal, and the generated programmable delay signal may comprise a reset signal.

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Soloman encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.

Abstract: A Continuous-Time Delta-Sigma Analog-to-Digital Converter (CT??ADC) for a radio frequency (RF) receiver employing a 200 kHz IF realizes an optimal signal-to-noise ratio using a programmable resonator that is set to resonate at 200 kHz. The programmable resonator is operably coupled to receive both an analog input signal at a low IF of 200 kHz and an analog feedback signal. From the analog input signal and the analog feedback signal, the programmable resonator produces a resonate signal at the low IF, and provides the resonate signal to a quantizer. The quantizer produces a digital output having a digital value coarsely reflecting an amplitude of the analog input signal. The CT??ADC further includes at least one programmable digital-to-analog converter (DAC) operably coupled to receive the digital output and to convert the digital output into the analog feedback signal provided to the programmable resonator.

Abstract: A method and apparatus for efficiently deriving modulo arithmetic solutions for frequency selection in transceivers. A frequency for communication between a wireless user interface device and a wirelessly enabled host is generated by calculating a modulo solution for an input variable. In some embodiments of the invention, the communication between the user input device and the wirelessly enabled host complies with the Bluetooth wireless communication standard. For the embodiments of the present invention relating to communications systems implementing the Bluetooth standard, a method and apparatus is disclosed for generating communication frequencies based on modulo 23 and modulo 79 solutions input variables. The method and apparatus of the present invention can generate the communication frequency with a minimum number of calculations using simple binary addition, as opposed to prior art methods that generally require numerous iterations and complex calculations.

Abstract: Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. A means for decoding LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addition). By appropriate modification of the various calculations that need to be performed when updating edge messages, the calculations may be reduced to only performing product of terms functions. When implementing such functionality in hardware within a communication device that is operable to decode LDPC coded signals, this reduction in processing complexity greatly eases the actual hardware's complexity as well. A significant savings in processing resources, memory, memory management concerns, and other performance driving parameters may be made.

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a packet data transfer circuit that uses a fragment storage buffer to align and/or merge data being transferred to or from memory on a plurality of channels. In a packet reception embodiment, a data shifter and fragment store buffer are used to align received packet data to any required offset. The aligned data may and then be written to the system bus or combined with data fragments from prior data cycles before being written to the system bus. When packet data is being transferred to memory on a plurality of channels, the fragment storage may be channelized using register files or flip-flops to store intermediate values of packets and states for each channel.

Abstract: A Radio Frequency (RF) receiver includes a low noise amplifier (LNA) and a mixer coupled to the output of the LNA. The gain of the LNA is adjusted to maximize signal-to-noise ratio of the mixer and to force the mixer to operate well within its linear region when an intermodulation interference component is present. The RF receiver includes a first received signal strength indicator (RSSI_A) coupled to the output of the mixer that measures the strength of the wideband signal at that point. A second received signal strength indicator (RSSI_B) couples after the BPF and measures the strength of the narrowband signal. The LNA gain is set based upon these signal strengths. LNA gain is determined during a guard period preceding an intended time slot of a current frame and during a guard period following an intended time slot of a prior frame. The lesser of these two LNA gains is used for the intended time slot of the current frame.