Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been generated using combined LDPC coding and modulation encoding to generate LDPC coded modulation signals. In addition, the bit metric updating is also extendible to decoding of LDPC variable code rate and/or variable modulation signals whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. By ensuring that the bit metrics are updated during the various iterations of the iterative decoding processing, a higher performance can be achieved than when the bit metrics remain as fixed values during the iterative decoding processing.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: A charge pump includes a resistor divider connected between an output voltage node and ground and a comparator inputting a reference voltage at one input, and a divided voltage from the resistor divider at another input. A digital control circuit is enabled by the comparator. A first transistor and a second transistor are in series between an input voltage node and the ground, both transistors controlled by the digital control circuit. A pump capacitor is connected between to the output voltage node and between the first and second transistor, and being charged by turning the first and second transistors on and off. A first diode is between the pump capacitor and the input voltage node. A second diode between the pump capacitor and the output voltage node. A reservoir capacitor between the output voltage node and ground. The digital control circuit comprises a first shift register.

Abstract: A system, method and apparatus for reducing a power consumed by a physical layer device (PHY). A length of a cable connecting the PHY to a link partner is determined. Based on the length, power provided to one or more components of the PHY, or any portion thereof, is reduced. The power provided is reduced while maintaining a level of reliability specified by a protocol governing operation of the PHY. The length can be determined using time-domain reflectometry (TDR) techniques. Any portion of an echo cancellation filter, a crosstalk filter, an equalizer, a precoder, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a forward error correction (FEC) decoder and/or an FEC coder can be powered-down or power-optimized to reduce the overall power consumed by the PHY. The protocol governing operation of the PHY can be IEEE 802.3.

Abstract: A data communication network for providing dynamic routing through both wireless and wired subnetworks to support wireless communication devices and wired remote stations is disclosed. In the wireless network, the wireless communication devices can be mobile RF terminals, while the wired remote stations might be personal computers attached to a wired subnet, such as an ethernet coaxial cable. The wireless network architecture utilizes a spanning tree configuration which provides for transparent bridging between wired subnets and the wireless subnets. The spanning tree configuration provides dynamic routing to and from wireless communication devices and remote stations attached to standard IEEE 802 LANs.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: Systems and methods that provide fault tolerant transmission control protocol (TCP) offloading are provided. In one example, a method that provides fault tolerant TCP offloading is provided. The method may include one or more of the following steps: receiving TCP segment via a TCP offload engine (TOE); calculating a TCP sequence number; writing a receive sequence record based upon at least the calculated TCP sequence number to a TCP sequence update queue in a host; and updating a first host variable with a value from the written receive sequence record.

Abstract: A system and method for handshaking multiple xDSL technologies is provided. More particularly, the present invention provides a means for new xDSL technologies such as VDSL to negotiate usage of bidirectional frequencies while maintaining backward compatibility with legacy, i.e. non-VDSL modems. In an embodiment, a central office modem configured to operate using VDSL technology provides a modified signal to a remotely located modem. The modified signal provides capability indicators to the remotely located modem that indicate the central office modem is able to use the VDSL bidirectional frequencies. However, the modified signal also maintains sufficiently similar characteristics to traditional capability indicators so that it can be interpreted by legacy modems.

Abstract: A voltage regulator includes a first stage capable having a first current flowing through it. A second stage has a second current. A third stage is capable of outputting an output voltage and has a third current flowing through it. The first, second and third currents are proportional to each other throughout a range of operation of the voltage regulator between substantially zero output current and maximum output current. The first stage drives the second stage as a low input impedance load.

Abstract: An adaptive receiver is disclosed for optimally receiving and processing signals. The receiver utilizes one or more memory blocks to store groups of incoming symbols. The groups of symbols are processed by a channel estimation subsystem to determine channel characteristics. The receiver determines the appropriate demodulation and decoding strategy to implement based on the determined channel characteristics. The receiver includes a plurality of demodulation and decoding schemes, one of which is selected based on the results of a channel estimation analysis.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning a local oscillation frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset.

Abstract: A method and apparatus for an image canceling digital-to-analog converter is disclosed. Up-sampling and noise shaping is used to produce a stream of digital sample values at a relatively higher sampling rate than the sampling rate of the digitized input samples, each higher sampling rate sample having fewer bits than the original samples. The higher sampling rate stream is then distributed for sequential conversion by multiple digital-to-analog converters each operating at a lower sampling rate. The outputs of the converters are then combined to form a combined output signal. Most spectral images normally observed in a standard or conventional DAC are attenuated in the combined output signal of an embodiment in accordance with the present invention. Any spectral images that remain are further from the signal of interest, permitting the use of lower cost filtering.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: Methods and systems are provided for non-cryptographic capabilities of a token such as a smartcard to be used as an additional authentication factor when multi-factor authentication is required. Smartcards are configured to generate a transaction code each time a transaction is attempted by the smartcard. The transaction code is dynamic, changing with each transaction, and therefore is used as a one-time password. When a user attempts to access a service or application requiring at least two authentication factors, a secure processor is used to read transaction code from the smartcard. The secure processor establishes a secure communication with the remote computer hosting the service or application. The transaction code can then be encrypted prior to transmission over the public Internet, providing an additional layer of security.

Abstract: A system and method for performing frame loss concealment (FLC) when portions of a bit stream representing an audio signal are lost within the context of a digital communication system. The system and method utilizes a plurality of different FLC techniques, wherein each technique is tuned or designed for a different kind of audio signal. When a frame is lost, a previously-decoded audio signal corresponding to one or more previously-received good frames is analyzed. Based on the result of the analysis, the FLC technique that is most likely to perform well for the previously-decoded audio signal is chosen to perform the FLC operation for the current lost frame. In one implementation, the plurality of different FLC techniques include an FLC technique designed for music, such as a frame repeat FLC technique, and an FLC technique designed for speech, such as a periodic waveform extrapolation (PWE) technique.

Abstract: A universal authentication token is configured to securely acquire security credentials from other authentication tokens and/or devices. In this manner, a single universal authentication token can store the authentication credentials required to access a variety of resources, services and applications for a user. The universal authentication token includes a user interface, memory for storing a plurality of authentication records for a user, and a secure processor. The secure processor provides the required cryptographic operations to encrypt, decrypt, and/or authenticate data that is sent or received by universal token. For example, secure processor may be used to generate authentication data from seed information stored in memory.

Abstract: An embodiment of the present invention provides a wireless telephone including a receiver module, a channel decoder, a speech decoder, and a speaker. The receiver module receives a plurality of versions of a voice signal, wherein each version of the voice signal comprises a plurality of speech frames. The channel decoder is configured to decode a speech parameter associated with a first speech frame from a first version of the voice signal, wherein decoding the speech parameter includes selecting an optimal bit sequence from a plurality of candidate bit sequences and wherein the selection of the optimal bit sequence is based in part on a second speech frame from a second version of the voice signal. The speech decoder decodes at least one of the first or second versions of the voice signal based on the speech parameter to generate an output signal. The speaker receives the output signal and produces a sound pressure wave corresponding thereto.

Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: Non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation). A non-systematic and non-linear PC-TCM code is presented that provides quite comparable performance to turbo encoding using only systematic and linear trellis codes (e.g., convolutional codes). The non-systematic and non-linear PC-TCM described herein may be modified to support a wide variety of code rates (e.g., rate 2/3, 5/6, 8/9, and 3/4 among other rates) and also a wide modulation types (e.g., 8 PSK (8 Phase Shift Key) and 16 QAM (16 Quadrature Amplitude Modulation) among other modulation types). In one embodiment, a non-systematic and non-linear PC-TCM presented herein comes to within approximately 0.15 dB of a systematic and linear turbo code. A design approach is presented that allows for the design of such non-systematic and non-linear PC-TCM codes and several exemplary embodiments are also presented that have been designed according to these presented principles.