Abstract: A system and method for increasing bandwidth usage between an access point and a wireless device are described. One embodiment can include an access point, a prioritizer, and a priority storage device. These components can increase bandwidth usage between an access point and a wireless device by allocating previously unused transmission slots.

Abstract: A multimode wireless communication device includes a first circuit having a digital baseband processing module to convert outbound data into outbound digital baseband signals and to convert inbound digital baseband signals into inbound data, an analog to digital converter module to convert inbound analog baseband signals into the inbound digital baseband signals, and a digital to analog converter module to convert the outbound digital baseband signals into outbound analog baseband signals. A second circuit includes a first radio section and a third circuit includes a second radio section. A diversity antenna arrangement includes a first antenna, a second antenna, a first diplexer coupled to the first antenna, and a second diplexer coupled to the second antenna, that selectively couples the first radio section to one of the first antenna and the second antenna, and that selectively couples the second radio section to one of the first antenna and the second antenna.

Abstract: A system includes a first transmitter, a second transmitter, and a legacy receiver. The first transmitter transmits information via a first channel to the legacy receiver. The second transmitter transmits a time-shifted version of the information via a second channel to the legacy receiver. The legacy receiver combines the information received via the first channel and the time-shifted information received via the second channel to provide combined information. The legacy receiver processes the combined information as though it is received via a single channel.

Abstract: An imaging device includes a plurality of photo-diodes that operate as optical pixels arranged in a plurality of columns on a single CMOS substrate. The outputs of the multiple pixel sensors, or photo-diodes, are examined to determine if a one pixel, or a region of pixels are in saturation. If so, then the pixel gain is adjusted to correct or compensate for the image distortion in the region. For example, the gain of the charging amplifier or operational amplifier can be adjusted to correct for saturation. This can be done in real-time since hardware is being tuned for the correction instead of software.

Abstract: The present invention includes a method of determining a phase estimate for an input signal having pilot symbols. The method includes receiving a plurality of pilot symbols, and then multiplying two or more pilot symbol slots by corresponding correlator coefficients to correct a phase estimate of the input signal.

Abstract: A method and apparatus for the detection and correction of large carrier offsets. A set of known correction carrier offsets are used to translate an input signal having a carrier offset. After applying each correction carrier offset, a state of a timing recovery loop is evaluated. The set of known correction carrier offsets are sequentially used to translate the input signal until the timing recovery loop is locked. The carrier offset is substantially acquired when the timing recovery loop is locked.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down converted to base band frequencies and base band signals to be up converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning the LO frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset.

Abstract: A wireless terminal implements location-based transaction authentication and includes a wireless interface, a user interface, a Global Positioning System (GPS) receiver, and a processing unit. The wireless terminal receives a transaction request from the user, accesses a servicing network via the wireless interface, sends a transaction initiation request to the servicing network, receives an authentication challenge from the servicing network, and determines its current location via access of the GPS receiver. The wireless terminal prepares and transmits an authentication response based upon the received location. When the authentication response is accepted by the servicing network, the processing unit is able to service the transaction between the user and the servicing network. When the authentication response is rejected the transaction is not serviced. Relative location information and further user authentication may also be used.

Abstract: An electrostatic-discharge/impedance-matching circuit for use in radio frequency (RF) integrated circuits. The electrostatic-discharge/impedance-matching circuit includes at least one shunt circuit operable to shunt current related to an over-voltage condition and at least one series element operably coupled to the shunt element. The shunt element and series element in combination provide electrostatic discharge protection for the RF signal processing circuit elements on the integrated circuit and also provide a matched input impedance for an incoming RF signal. Various alternate embodiments of die electrostatic-discharge/impedance-matching circuit include first and second shunt elements and a series element operably connected in combination to provide optimal electrostatic discharge protection and impedance matching.

Abstract: A fault tolerant method transforms physically contiguous data in-place on a disk by partitioning the physically contiguous data into an empty region physically adjacent to data regions including a first data region and a last data region, the first and last data regions at opposing ends of the physically contiguous data regions. The physically contiguous data are transformed in an order beginning with the first data region and ending with the last data region. The transforming step perform first locking and reading the first data region, second, transforming the first data region, third, writing and unlocking the transformed first data region to the empty region, and fourth, declaring the first data region as the empty region while declaring the empty region as the first region. The first through fourth steps are repeated for each data region, until completion, to transform the physically contiguous data in-place on the disk.

Abstract: Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and discrete-time delta-sigma modulators, and digital and/or analog feedback loops. One or more processes are performed in a pipeline having a higher throughput rate than a throughput rate of a delta-sigma modulator. Any of a variety of processes and combinations of processes can be performed in the pipeline including, without limitation, quantization, digital signal processing, and/or feedback digital-to-analog conversion.

Abstract: The present invention relates to systems and methods for programming a memory cell. More specifically, the present invention relates to a controlled application of current to a memory cell over a controlled time period. The invention utilizes a current mirror configuration having a first transistor and a second transistor, wherein the second transistor is coupled to the memory cell. Programming of the memory cell includes applying a voltage to the first transistor, whereby a first current is generated in the first transistor. A gate of the second transistor is coupled to the first transistor, whereby a second current is generated in the second transistor. The second current is proportional to the first current. The second current is provided to the memory cell, whereby the second current programs the memory cell.

Abstract: A method for selectively controlling the flow of data through a network device is discussed. The network device has a plurality of ports, with each port of the plurality of ports having a plurality of priority queues. Congestion at one priority queue of the plurality of priority queues is detected and a virtual channel message is sent to other network devices connected to the network device causing data destined for the one priority queue to be halted. After the congestion at the one priority queue has abated, a virtual channel resume message is sent to the other network devices.

Abstract: Aspects of a method and system for a linear regulator with high bandwidth, PSRR, and a wide range of output current are provided. A method for isolating voltages in a circuit may comprise applying a reference voltage to an isolation resistor based on a supply voltage. An internal voltage at a reference point may be determined based on the applied reference voltage, and a maximum and/or minimum voltage may be determined based on the internal voltage. A plurality of output transistor devices may be controlled based on either the maximum voltage or minimum voltage. The reference voltage may be modified based on controlling the plurality of output transistor devices. By turning ON and OFF the output transistor devices, a much wider operating range is facilitated.

Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes a heat spreader cap defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. A planar rim portion of the cap that surrounds the cavity is coupled to the leadframe. The cap and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.

Abstract: A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit board formed by a plurality of substantially partially overlapping bores. An electrically conductive plating is formed on an inner surface of the opening. The plating forms a plurality of distinct electrically conductive paths.

Abstract: An update algorithm for equalizer coefficients in a communications system using phase correction symbols. Instead of using a traditional all symbols slicer update algorithm, the equalizer is updated during phase correction symbols for optimal performance in low signal-to-noise ratio conditions. In lower signal-to-noise ratio conditions, the equalizer uses a phase correction circuit to compensate for distortion caused by a communication channel when a demodulated data stream contains an unknown phase offsets resulting from a fast dynamic distortion. More specifically, the phase correction circuit uses a phase correction signal to correct for the unknown phase offsets in a demodulated data stream in lower signal-to-noise ratio conditions. The equalizer then corrects for distortion caused by the communication channel based upon the phase corrected demodulated data stream.

Abstract: A high-quality, low-complexity audio time scale modification (TSM) algorithm useful in speeding up or slowing down the playback of an encoded audio signal without changing the pitch or timbre of the audio signal. The TSM algorithm uses a modified synchronized overlap-add (SOLA) algorithm that maintains a roughly constant computational complexity regardless of the TSM speed factor and that performs most of the required SOLA computation using decimated signals, thereby reducing computational complexity by approximately two orders of magnitude.

Abstract: A system (50) includes a communication path (170) and transmits data on a network (103, 106). A transmitter (101) transmits data on the network and a receiver (112) receives data from the network. A component (102, 114) in the communication path has a transfer characteristic (C1, C2, C3) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.

Abstract: The present invention provides a system, method and apparatus for encrypting/decrypting plain data/cipher text having lengths not equal to a multiple of a data chunk of a block cipher algorithm. The present invention enables plain data having a length that is greater than or less than one data chunk to be encrypted to produce an encrypted version of the plain data having the same length. Further, the present invention enables cipher text having a length that is greater than or less than one data chunk to be decrypted to produce a decrypted version of the cipher text having the same length. Decryption of cipher text having a length that is greater than one data chunk uses two rounds of decryption. A first round of decryption recovers an indirectly encrypted portion. A second round uses the indirectly encrypted portion to completely recover the original plain data.