Abstract: A method and system for VCO with switchable varactor for low KVCO variation is provided. Aspects of a method for controlling a signal may comprise controlling an oscillating frequency of a time varying signal in a circuit, and controlling a change in the oscillating frequency based on switching of a plurality of varactors. The switching of the varactors may control a change in the oscillating frequency based on a control voltage. The method may further comprise minimizing a change in the rate of change in the oscillating frequency based on the switching of the varactors. Aspects of a system for controlling a signal may comprise circuitry that controls an oscillating frequency of a time varying signal in a circuit, and circuitry that controls a change in the oscillating frequency based on switching of a plurality of varactors. An executable computer program may cause a machine to execute steps as described above.

Abstract: Certain embodiments of the invention may be found in a method and system for monitoring a set of semaphore registers using a limited-width test bus. Each semaphore register represents a separate hardware resource. The bits in a semaphore register are monitored jointly to determine whether the hardware resource it represents is in use by a software thread. The bits in the same register bit location of all the semaphore registers are monitored jointly to determine the ID number of the software thread currently using the hardware resource. The limited-width test bus comprises of bit lines representing each semaphore registers and bit lines representing the contents of the semaphore registers. Semaphore protocol steps are used in addition to changes monitored by the limited-width test bus to determine current usage of each hardware resource and to identify the ID number of the software thread using a hardware resource.

Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: A system and method for providing quality-of-service based network resource allocation and utilization in a dynamic network environment. For example, a wireless communication network may comprise a first system and a second system. The first system may provide a current service to a user at a current quality level. The first system and second system may establish a wireless communication link. At least one of the first and second systems may determine whether utilizing one or more resources of the second system will provide the current service to the user at a higher level of quality than the current quality level. One or more resources of the second system may be allocated for providing the current service to a user at a higher quality level. The allocated resources may be utilized to provide the current service to the user at a higher quality level than the current quality level.

Abstract: The present invention relates to a system and method for equalizing the capacitance between/among n lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the n lines using an algorithm for example. After determining the twisting pattern forming at least n?1 twisted sections, the n lines are twisted according to the pattern so that each of the n lines runs along every other line for a same distance across the length of a bus.

Abstract: An end-point device comprises multiple transceivers via which the end-point device associates with multiple access points simultaneously. The access points may belong to communicatively incompatible packet switched data networks. A backbone network communicatively connects all associated access points. The end-point device receives unique network address of an access point from the access point upon association and sends network addresses of other currently associated access points and first rule information to the access point either upon association or prior to detaching from the access point. One or more of the other currently associated access points may direct above action of the end-point device. The end-point device or one of the other access points generates the first rule information.

Abstract: A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low passn filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feed back path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator. The rotation speed of the phase rotator is controlled by an accumulator and a digital frequency control word.

Abstract: End point device interacts directly and/or indirectly both with a first node using a first protocol and a second node using a second protocol. In one embodiment, the first node and the second node are access points. The second node does not have first node network address even if it is communicatively coupled to the first node via an alternate upstream path. The first node does not know second node network address. The end point device has the first node network address and the second node network address. The second node sends data destined for the first node to the downstream end point device. The end point device applies necessary coding, formatting and/or encryption to the data before delivering the data to the first node using the first node network address if the first protocol is different from the second protocol. Else the end point device forwards the data to the first node. The end point device in addition acts as a bridge for data from the first node to the second node.

Abstract: A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner perimeter of the N-well surrounds at least a portion of the active region of the PMOS device. According to an embodiment, the inner perimeter of the N-well surrounds the entire active region. The PMOS device can include a deep N-well in contact with the N-well.

Abstract: A method of controlling power levels on a plurality of transmit streams in a single radio transceiver includes, for each of the plurality of transmit streams, detecting an output power level and sampling the output power level, digitizing the sample output power level, producing the digitized sample to a baseband processor. The baseband processor is operable to perform rate based compensation on the digital sample, to integrate and dump a plurality of digitized samples over a period that exceeds a transmission frame period to produce an average value over a specified number of samples. Thereafter, the processor is operable to convert the integrated plurality of digitized samples to a normalized value and to comparing the normalized value to a target value to generate a power index value to determine an output power level with rate based compensation.

Abstract: An end-point device comprises multiple communication transceivers via which the end-point device associates with multiple access points. The multiple access points may belong to packet switched data networks that are communicatively incompatible. Each of the associated access points contributes a separate pathway for flow of data packets from the end-point device to a destination device. The end-point device gathers information regarding the associated pathways. The information may contain protocol information, user preferences and/or current pathway performance information. The end-point device uploads unique network addresses assigned to it by the associated access points and the gathered information to all or selected few of nodes of the associated networks. If needed, the end-point device associates with an additional access point or dissociates from an access point.

Abstract: An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

Abstract: Analog signal paths are utilized between a baseband processor and a radio front end to support high throughput communications for a multiple in multiple out radio transceiver that support communications over two or more antennas. Specifically, analog differential I and Q path communication signals are exchanged between a radio front end core and a baseband processor to maximize throughput capacity for high data rate signals. Along the same lines, the impedances of traces and the interface are matched to reduce I/Q imbalance.

Abstract: An apparatus and method for reducing an average power consumed by an iterative decoder. A power savings loop coupled to the iterative decoder includes an averager, a comparator and an integrator. The averager receives an iteration count from the iterative decoder and determines an average iteration count of the iterative decoder. The comparator compares the average iteration count to a threshold. The threshold corresponds to a noise level that exceeds a level of noise associated with a quasi-error free (QEF) operating point of the iterative decoder. When the average iteration count exceeds the threshold, the integrator produces an output signal that lowers the maximum number of permissible iterations the iterative decoder can conduct. As a result, the average iteration count is lowered, thereby reducing the average power consumed by the iterative decoder.

Abstract: An apparatus and method for a low voltage drop and thermally enhanced integrated circuit (IC) package are described. A substantially planar substrate having a plurality of contact pads on a first surface is electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate. An IC die having a first surface is mounted to the first surface of the substrate. The IC die has a plurality of I/O pads electrically connected to the plurality of contact pads on the first surface of the substrate. A heat sink assembly is coupled to a second surface of the IC die and to a first contact pad on the first surface of the substrate to provide a thermal path from the IC die to the first surface of the substrate. The heat sink assembly can also provide an electrical path from the IC die to the first surface of the substrate. The heat sink assembly may have one or two heat sink elements to provide thermal and/or electrical connectivity between the IC die and the substrate.

Abstract: An integrated circuit radio transceiver and method therefor is operable to flexibly and efficiently de-interleave a received communication signal by initially changing a received signal from the time domain to the frequency domain to generate a plurality of tones that are then rearranged in a first de-interleaving step to an order expected by a downstream decoder. Thereafter, the tones are detected to generate a soft bit sequence and are then reverse-swizzled and de-interleaved. The de-interleaving step is performed in a manner that compensates for row/column offset interleaving performed by a transmitter that transmitted the received signal being processed.

Abstract: Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in accordance with the present invention apply a variety of techniques that may include, in various applications, collapsing two multi-round authentication algorithm (e.g., SHA1 or MD5 or variants) processing rounds into one; reducing operational overhead by scheduling the additions required by a multi-round authentication algorithm in such a matter as to reduce the overall critical timing path (“hiding the ads”); and, for a multi-loop (e.g., HMAC) variant of a multi-round authentication algorithm, pipelining the inner and outer loops.

Abstract: A method includes an access point providing a request for co-location interference information to at least one multiple protocol device. The method continues with the at least one multiple protocol device obtaining co-location interference information in response to the request. The method continues with the at least one multiple protocol device providing the co-location interference information to the access point.

Abstract: An end point device that interacts with a first access point using a first radio and via a first direct pathway. The end point device interacts with at least a second access point using a second radio and via a second direct pathway. The end point device sends multimedia information packets and command packets meant for the first access point via the first direct pathway and using the second radio respectively. The first access point and the second access point are communicatively coupled via a plurality of communicatively incompatible packet switched data networks. The command packets reach the first access point traveling via the second direct pathway, the second access point and the plurality of packet switched data networks. The first access point responds to the command packets by causing a change in performance of the first radio and performance of the first direct pathway.

Abstract: A receiver includes digital logic for defining a plurality of signal paths for an ingoing digital signal to determine a frame classification. Frames are classified according to a combination of readings of a plurality of correlation block and relative signal (power) strengths. Power detection is specified for frequency bands of interest. The combination of readings and their corresponding pattern may be used to determine whether a frame is being transmitted in a lower bandwidth channel, an upper bandwidth channel or a large bandwidth channel that overlaps the lower and upper bandwidth channels. A transmission type (legacy, mixed mode, Greenfield) may subsequently be determined based upon the identity of the frame channel.