Abstract: A transceiver includes a Downstream Signal Processor (DSP), an Upstream Signal Processor (USP), a Local Oscillator (LO), a differencer, a reference signal generator, and an estimator. The DSP receives an initial downstream signal, a downstream LO signal from the LO, and from the estimator a frequency-offset estimate indicative of a free-running frequency offset included in the initial downstream signal. The DSP uses the LO signal and the estimate to frequency down-convert the initial downstream signal, and also to remove the frequency offset from the initial downstream signal, thereby producing a corrected downstream signal. The USP uses both an upstream LO signal from the LO and the estimate to frequency convert an initial upstream signal so as to produce a frequency pre-corrected upstream signal.

Abstract: A programmable LED display system is disclosed. The system includes a programmable controller; a driver operative to generate a control signal in response to a signal provided by the programmable controller; and a display device operative to provide a visual representation of the state of the system in response to the control signal. The system also includes means for determining which state condition is displayed when more than one state condition exists.

Abstract: A system and method for increasing bandwidth usage between an access point and a wireless device are described. One embodiment can include an access point, a prioritizer, and a priority storage device. These components can increase bandwidth usage between an access point and a wireless device by allocating previously unused transmission slots.

Abstract: One or more methods and systems of providing a conditioned power source to an external card that is communicatively connected to a host computing device by way of an external card adaptor are presented. The system and method facilitates the use of an external card having a connector that is incompatible with a PC card connector provided by the host computing device. In one or more embodiments, the external card adaptor performs power conditioning and/or voltage conversions of one or more power signal inputs provided by the host computing device. The power conditioning is performed using a power conditioning circuitry while the voltage conversions are performed using a voltage conversion circuitry.

Abstract: A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: A method is disclosed for correcting carrier frequency offset (CFO) in a received data packet that includes one or more M data streams. The data packet has a payload portion preceded by a preamble portion, the payload portion having a plurality of data symbols (L) each of which include a plurality of data tones (K). The method comprises, making a per-stream preamble CFO estimate for each data stream by correlating repeated preamble portions that precede the data packet. The per-stream preamble CFO estimates are weighted and averaged to obtain a single preamble CFO estimate. Any CFO in each received data stream is then corrected according to the preamble CFO estimate. Additionally, for an lth data symbol in a data packet, a per-tone CFO estimate is derived and successively averaged over frequency (tones), time (symbols) and space (data steams) to derive data CFO estimate pdata. Any CFO in each received data stream may be corrected according to the data CFO estimate, and/or the preamble CFO estimate.

Abstract: A baseband controller system creates and maintains a schedule of synchronized events and reviews the schedule as a part of determining whether to initiate a transmission of a non-synchronous event. One aspect is to avoid a possibility of collision between synchronized and non-synchronized communication events. The schedule of synchronized events are evaluated in relation to the present time and determine whether a non-synchronized event may be transmitted without the likelihood of a collision. The transmission determination includes evaluating future time periods to see if a synchronized event is scheduled during a time period in which the non-synchronized event would continue to be transmitted for those non-synchronized events that span two or more defined time periods in length.

Abstract: A system, method and computer program product is provided for caching domain name system (DNS) information on a network gateway. In particular, a network gateway that interfaces one or more customer premises equipment (CPE) devices to an IP network maintains a centralized on-board cache for storing domain names and corresponding IP addresses. The domain names and IP addresses in the cache are used by the network gateway to resolve DNS queries generated by application programs running on the CPE devices in a manner that is transparent to the CPE devices and that does not expend CPE resources. The cache may be initially loaded by an attached CPE or an external network entity and is continuously populated with information extracted from DNS messages exchanged between a CPE device and the external IP network.

Abstract: One or more methods and systems of resynchronizing or dynamically retuning a clock signal over a high speed clocked data interface are presented. In one embodiment, the system and method utilizes first and second delay lines, a first pair of digital logic devices to generate a first data sequence, a second pair of digital logic devices to generate a second data sequence, a memory, a set of software instructions resident in the memory, a processor, and a user interface. The first and second data sequences are input into a digital logic circuit that compares the two sequences and generates an output. The output is clocked into a digital logic device to generate an indicator signal that is used to resynchronize or dynamically re-tune the clock signal.

Abstract: A system (50) includes a communication path (170) and transmits data on a network (103, 106). A transmitter (101) transmits data on the network and a receiver (112) receives data from the network. A component (102, 114) in the communication path has a transfer characteristic (C1, C2, C3) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.

Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes a first arm, a second arm, and a via. The first arm has a first end and a second end. The second arm has a third end and a fourth end. The first arm and the second arm intersect and the first, second, third and fourth ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the first and second arms.

Abstract: A clock generator includes an active oscillator portion that generates an oscillating signal having a frequency determined by a resonator, such as a crystal or other type of resonator. A filter or delay module filters or delays the oscillating signal to generate a second oscillating signal that has a DC component that matches that of the original oscillating signal. A comparator then compares the original oscillating signal with the filtered or delayed oscillating signal to determine the amplitude cross points. In other words, the comparator determines where the amplitude of the original oscillating signal crosses that of the filtered or delayed oscillating signal, and generates a square wave pulse at the amplitude cross points. Since both compared signals have a common DC component then the amplitude cross points will be equally separated in time, which produces an output oscillating signal with a 50% duty cycle.

Abstract: Efficient LDPC code decoding with new minus operator in a finite precision radix system. A new mathematical operator is introduced and applied to the decoding of LDPC coded signals. This new operator is referred to as the min†? (min-dagger minus) operator herein. This min†? processing is appropriately applied during the updating of the edge messages with respect to the variable nodes. In a bit level decoding approach to decoding LDPC coded signals, the updating of the edge messages with respect to the bit nodes is performed using the new min†? operator. This approach provides very comparable performance to min** processing as also applied to updating of the edge messages with respect to the bit nodes and may also provide for a significant savings in hardware. Also, within finite precision radix systems, the new min†? operator provides a means by which always meaningful results may be achieved during the decoding processing.

Abstract: A method and associated system for effectively increasing the number of antenna elements within a multi-element antenna system through computation of a response of “virtual” antenna elements located along an antenna array. The physical elements of the array are positioned sufficiently near each other to enable synthesis of a polynomial or other mathematical expression characterizing the response of the array to receipt of an incident waveform. Values of the responses associated with the virtual antenna elements of the array may then be determined through evaluation of the synthesized polynomial or other expression. The resultant array response values associated with the virtual and physical elements of the array are then provided to an associated receiver for processing.

Abstract: A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive parallel data via a network connection. The transmitter is operably coupled to convert outbound parallel data from the network interface processor into serial transmit data. The receiver is operably coupled to convert serial receive data into inbound parallel data, wherein the receiver provides the inbound parallel data to the network interface processor.

Abstract: A location tracking apparatus and method are disclosed. In one embodiment, the method comprises receiving information from each repeater indicating which packets wirelessly transmitted by a mobile station were received by each repeater including received signal strength of each of those packets, and determining location of the mobile station with respect to the repeaters based on power levels of individual wirelessly transmitted packets received at the repeaters.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: A combined sidetone and hybrid balance apparatus and method of operating same are disclosed. An embodiment of the present invention may provide both a hybrid balance mode of operation and a sidetone generation mode of operation within a single integrated circuit device. The functionality provided by an embodiment of the present invention may be used in both Internet protocol (IP)-based telephones and residential gateways, and may be incorporated within the IP telephone chip used in such devices. An embodiment of the present invention may be used to reduce processor demand and the cost of materials, permitting greater IP telephone or residential gateway functionality at lower cost.

Abstract: Provided is a system and method for performing CRC analysis in a video test bench. An exemplary system includes a memory configured for storing a required number representative of the data fields to be analyzed. A module is coupled at least indirectly to the memory and configured for (i) receiving an input data stream, (ii) performing cyclic redundancy check (CRC) analysis of the received data stream, and (iii) producing an output representative of an actual number of received data fields analyzed. The input data stream includes synchronization markers defining boundaries of each of the received data fields. Next, a comparator is configured for (i) comparing the required number and the actual number and (ii) producing a disabling signal when the actual number matches the required number.