Abstract: Methods and apparatus are provided for handling data at a cryptography accelerator output interface. A shared resource such as a shared output buffer is provided at the cryptography accelerator output interface having multiple output ports. The output interface shared resource can be allocated amongst the various output ports based on characteristics and requirements of the various input ports. References to data in the shared resource allow processing and ordering of data following processing by cryptographic processing cores.

Abstract: Methods and apparatus are provided for handling data at a cryptography accelerator input interface. A shared resource is provided at the cryptography accelerator input interface having multiple input ports. The input interface shared resource can be allocated amongst the various input ports based on characteristics and requirements of the various input ports. References to data in the shared resource allow processing and ordering of data in preparation for processing by cryptographic processing cores.

Abstract: Methods and apparatus are provided for sequencing data in a cryptography accelerator with multiple cryptographic processing cores. Cryptographic processing cores are grouped into blocks of cryptographic processing cores to efficiently process received data. Mechanisms are provided to order data sequences at both the cryptographic processing core block level and the cryptographic processing core level.

Abstract: Methods and apparatus are provided for decoupling a cryptography accelerator interface from cryptographic processing cores. A shared resource is provided at the cryptography accelerator interface having multiple input ports. References to data in the shared resource are provided to allow processing and ordering of data in preparation for processing by cryptographic processing cores without substantial numbers of separate buffers in the cryptographic processing data paths.

Abstract: A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an adder. In one embodiment, additional components are included in the system to ensure that underflow or overflow of the numerically controlled oscillator is prevented. In another embodiment, additional components are included to ensure that output pulses from the numerically controlled oscillator do not occur within a minimum time interval. The method includes deriving a phase adjustment factor, adding the phase adjustment factor to a frequency control word, providing the modified frequency control word to a numerically controlled oscillator and generating a phase shifted, frequency-locked output signal.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: A balancing/unbalancing (balun) structure for operating at frequency f1 includes a microstrip printed circuit board (PCB). A balun on the PCB includes two input ports are coupled to a differential signal. An isolated port is connected to ground through a matched resistance. An output port is coupled to a single-ended signal corresponding to the differential signal. A plurality of traces on the PCB connect the two input ports, the load connection port and a tap point to the output port. A f2 rejection filter on the PCB is wrapped around the balun and includes a first folded element with a transmission length of &lgr;2/4 and connected to the output port. A second folded element has a transmission length of &lgr;2/4 and connected to the tap point.

Abstract: A configurable multi-port modem includes a plurality of hybrids, a plurality of receivers, a plurality of transmitters, and a switching module. Each of the plurality of hybrids is operably coupled to provide 2 to 4 wire coupling for a corresponding one of a plurality of twisted pairs that are coupled to the configurable multi-port modem. Each of the plurality of receivers is operably coupled to convert inbound DSL signals into inbound data. Each of the plurality of transmitters is operably coupled to convert outbound data into outbound DSL signals. The switching module is operable to couple at least one of the plurality of hybrids to at least one of the plurality of receivers and to at least one of the plurality of transmitters based on a configuration control signal.

Abstract: A digital memory system (30) includes a memory cell (52), a bit line (50) and a charge integrity estimating module 35. The module is operative during a first mode of operation to detect whether a quantity of the charge stored in the memory cell lies within the first range of values or the second range of values, is operative during a second mode of operation to detect whether the quantity of the charge lies within a third range of values comprising a subset of the first range of values and is operative during a third mode of operation to detect whether the quantity of the charge lies within a fourth range of values comprising a subset of the second range of values.

Abstract: A printed antenna includes a 1st dipole section and a 2nd dipole section. The 1st dipole section includes a 1st radiation section and a 1st frequency section. The 2nd dipole antenna section includes a 2nd radiation section and a 2nd frequency section. The 1st and 2nd dipole antenna sections are electrically coupled together such that the currents flowing through the 1st and 2nd frequency sections substantially cancel and the current flowing through the 1st and 2nd radiation sections are substantially cumulative for a ½ wavelength antenna. For a full wavelength antenna, 1st and 2nd dipole antenna sections are electrically coupled together such that the currents flowing through the 1st and 2nd frequency sections are substantially cumulative and the current flowing through the 1st and 2nd radiation sections substantially cancel.

Abstract: An image data decoding system (2) is described in which a stream of compressed image data (1) corresponding to a plurality of image channels (ChA, ChB, ChC) each comprising intra-coded pictures (I) and inter-coded pictures (B, P) is received. A selected channel within the plurality of channels is fully decoded to produce display driving data. At least one non-selected channel is at least partially processed by the system even though it is not being displayed such that if a switch is made to that non-selected channel then display driving data for that newly selected channel can be produced without having to wait for the next intra-coded picture (I) to be received. The partial processing may take the form of merely buffering the compressed data for the non-selected channel. Alternatively, reference pictures or all pictures for the non-selected channel may be either fully decoded, or partially decoded to produce spatially sub-sampled versions of the pictures of the non-selected channels.

Abstract: A process of handling packet data in a packet buffer is disclosed. Free pointers are stored in a plurality of free pointer queues, with each of the plurality free pointer queues in a form of a linked list and the free pointers are retrieved from each of the plurality of free pointer queues and storing in a prefetch memory to provide a throughput of one free pointer per clock cycle. When an initial portion of a data packet is received, two free pointers are retrieved from the prefetch memory. One of the two free pointers is stored in a start pointer register connoting a start of the data packet and one free pointer is supplied for data elements of the data packet. One free pointer per middle data element is supplied, while no new pointer is needed for the end of packet data element.

Abstract: A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and accurate reference signal is established for receiving single-ended data.

Abstract: An electrically and thermally enhanced die-up ball grid array (BGA) package is described. An integrated circuit (IC) package includes a first substrate, a second substrate, and a stiffener. A surface of the first substrate is attached to a first surface of the stiffener. A surface of the second substrate is attached to a second surface of the stiffener. An IC die may be attached to a second surface of the second substrate or to the second surface of the stiffener. Additional electronic devices may be attached to the second surface of the second substrate.

Abstract: A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit board formed by a plurality of substantially partially overlapping bores. An electrically conductive plating is formed on an inner surface of the opening. The plating forms a plurality of distinct electrically conductive paths.

Abstract: A system includes a support device and an elongated spiral antenna coupled to the support device. The elongated spiral antenna has a contracted portion and an expanded portion. The expanded portion provides beam steering and directivity. The system also includes a feed line coupled to the elongated spiral antenna. A method for forming the elongated spiral antenna uses a predetermined formula to form arms of the elongated spiral antenna. The arms can be formed by printing the arms on a printed circuit board.

Abstract: Digital communications devices having high-speed add-compare-select circuits, and methods for designing the same. The add-compare-select circuits include logic segments separated by delay devices. The separation of the logic segments allows for pipelining of the add-compare-select processes and advantageous circuit retiming. The pipelining and advantageous circuit retiming permit the digital communications devices to be clocked at higher rates than similar digital communications devices having conventional add-compare-select circuits.

Abstract: A circuit is provided for reducing mismatches between the outputs of successive pairs of cells in an analog to digital converter A voltage input means is coupled to a first input terminal of each cell to introduce and an input voltage. A reference voltage means is coupled to a second input terminal of each cell to introduce progressive fractions of a reference voltage. A low impedance means is coupled between corresponding first output terminals and coupled between corresponding second output terminals in successive cells, to draw load-bearing currents to the successive cells, affecting the relative voltages and thereby reducing the effects of cell mismatches on these output terminals. Lastly, a high impedance means is coupled to the each of the first output terminals and to each of the second output terminals in successive cells.

Abstract: A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: Portable measuring devices which communicate by low power transceivers through a communication controller with a printer device collect weight and size data on articles to be shipped. The collected weight and size data are combined with origin and destination data, and labels are printed bearing pertinent shipping and routing information in machine readable format. The labels are attached to the articles to be shipped and accompany the articles to their respective destinations. At transfer points the labels are read by scanner devices which also communicate by low power transceiver links with the communication controller. The wireless linking of the scanner devices promotes human safety by the absence of cords which could cause entanglement of an operator in mechanized conveying equipment. The communication controllers at each stage of the shipping process have the capability of transferring received and updated status information on the shipped articles to a central data station.