Abstract: A signal recovery system and methods to quickly acquire signal lock and maintain consistent performance of the signal recovery system for different signal input rates of an input signal is provided. The system includes a phase locked loop system and a parameter controller. The method includes monitoring an input signal, determining a signal input rate of the input signal, providing shift factors to a loop filter contained within the signal recovery system, and adjusting the phase locked loop system performance based on the shift factors. The performance factors that can be modified include the acquisition rate, loop bandwidth, and damping factor of the phase locked loop system within the signal recovery system.

Abstract: A method and system for generating a graphical display from data describing at least one three-dimensional object is disclosed. The method and system include providing a plurality of processors and a single interpolator coupled with the plurality of processors. Each of the processors receive a portion of the data for one of the three-dimensional object(s), determine if a current position is located within the portion of the data, and provide an output if the current position is located within the portion of the data. The single interpolator is configured to provide information relating to characteristics of the portion of the data in the processor in response to the processor providing the output.

Abstract: An end user device is provided that supports a connection to a plurality of data communication networks. The end user device detects which data communication networks are available, and selectively determines which of the plurality of data communication networks provides the most optimal communication channel. The end user device also provides for seamless transitions between different data communication networks, thus permitting all network communication tasks to be performed in a seamless, uninterrupted manner regardless of the location of the device, the type of network connection being used, or the form of data communication being carried out. The end user device further provides for simultaneous communication over a plurality of data communication networks utilizing a single network identity.

Abstract: An integrated telephony controller circuit with the ability to perform auxiliary functions is disclosed. The invention consists of a coder-decoder circuit (CODEC) including at least one analog-to-digital converter (ADC), said CODEC being capable of sending and receiving telephony data signals; a multiplexer coupled to said ADC; and a receiving means for receiving an analog sense signal, said receiving means coupled to said multiplexer; wherein said multiplexer allows said telephony signals and said analog sense signal to share said ADC. This integrated circuit provides a state driven means to share the use of the ADC depending on whether the primary telephony function is active.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip blends graphics and video information by various graphics windows using alpha values for the windows, alpha values per pixel, or both. The chip calculates a composite alpha value based on the window's alpha values and the alpha values per pixel. Blended graphics and video may then be composited using the composite alpha value.

Abstract: Methods and systems for protecting integrated circuits (“ICs”) from power-on sequencing problems provide an interim voltage during power-on sequences in order to prevent over-voltage conditions across IC terminals. Voltages at first and second terminals of a circuit are monitored and an interim voltage to the second terminal is provided when the voltage at the first terminal exceeds a first threshold and a voltage at the second terminal is below a second threshold. The interim voltage protects the circuit from excessive voltage differences across the first and second terminals during power-on sequences, and is deactivated during normal operation so as not to draw excessive current. The method/system helps to insure that multi-supply dependent logic and/or other circuitry does not receive inappropriate voltage levels, and thus helps to insure that lower voltage level based circuitry is not damaged during power-up, transients, and/or glitches.

Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure.

Abstract: Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.

Abstract: The present invention relates to a system and method for providing distributed, highly configurable modular predecoding. The system includes a hierarchical memory structure, including a predecoder adapted to perform a first layer of address predecoding and at least one local predecoder interacting with the global predecoder and adapted to perform a second layer of address predecoding.

Abstract: A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to host computer formatted data separately from receiving the data packet. The network interface receives the data packet, converts the analog signal to a digitized signal, and stores the resulting sample packet in a storage queue. An off-line processor, which may be the host computer itself, performs the signal processing required to interpret the sample packet. In transmission, the off-line process converts host-formatted data to a digitized version of a transmission data packet and stores that in a transmission queue. A transmitter converts the transmission data packet format and transmits the data to the shared medium.

Abstract: A plurality of CMTS devices are linked together and synchronized to facilitate communication between the respective CMTS devices and respective downstream cable modems. According to one embodiment of the invention, one of the CMTS devices is designated as a master device, and the other CMTS devices are designated as slave devices. The respective CMTS devices are connected to each other by means of a synchronization bus. The master CMTS device then generates and broadcasts a future time stamp value, which is received by the respective slave CMTS devices. When the time stamp counter in the master CMTS device reaches the transmitted value, a control signal is broadcast over the synchronization bus. The slave CMTS devices then retrieve the time stamp value and reset their respective local time stamp counters to the received value. In this manner, the CMTS devices are synchronized.

Abstract: Driver circuits of the present invention provide current to drive laser diodes. The output current of the driver circuit includes a data signal and a low frequency tone signal. The low frequency tone signal is within the bandwidth of a power control feedback loop. The tone signal introduces low frequency noise into the output signal of the driver circuit. The low frequency noise causes jitter at the zero crossing points of the driver circuit output signal. A laser driver circuit of the present invention provides a compensation current to a laser diode. The compensation current is out of phase with the tone signal. The compensation current eliminates the low frequency noise in the output signal of the laser driver circuit.

Abstract: An on-chip differential multi-layer inductor includes a 1st partial winding on a 1st layer, a 2nd partial winding on the 1st layer, a 3rd partial winding on a 2nd layer, a 4th partial winding on the 2nd layer, and an interconnecting structure. The 1st and 2nd partial windings on the 1st layer are operably coupled to receive a differential input signal. The 3rd and 4th partial windings on the 2nd layer are each operably coupled to a center tap. The interconnecting structure couples the 1st, 2nd, 3rd and 4th partial windings such that the 1st and 3rd partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2nd and 4th partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined.

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract: A method of transmitting data in a cable modem system includes the steps of encoding the data using forward error correction. The data is then encoded with Turbo encoding. The data is then sent to a modulation scheme. The data is then transmitted over a cable channel. The data is then demodulated. The data is then decoded using a Turbo decoder. An inverse of the forward error correction is then applied to the data.

Abstract: A video encoding system includes a video source providing a multiple frame video signal, a compressed data interface, a host interface and a video encoding device. The video encoding device includes a video input processor, a global controller, a motion estimation processor, a digital signal processor and a bit-stream processor. The video input processor receives the video signal. The global controller controls the global operation of the video encoding device. The motion estimation processor is connected to the global controller. The digital signal processor is connected to the global controller and to the motion estimation processor. The bit-stream processor is connected to the digital signal processor, the global controller and the compressed data interface. The global controller stores encoding commands received from the host interface thereby programming the video input processor, the motion estimation processor, the digital signal processor and the bit-stream processor.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a circuit switched network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the circuit switched network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the circuit switched network for transmission on the packet based network, and re-modulating data signal packets from the packet based network for transmission on the circuit switched network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: An operational amplifier includes a first stage with a first differential transistor pair inputting a differential input signal at their gates, a first tail current source transistor connected to sources of the first differential transistor pair, and a load transistor pair connected in series with the drain of first differential transistor pair. An input stage includes a second differential transistor pair connected to respective drains of the first differential transistor pair at their gates, and a second tail current transistor connected to sources of the differential transistor pair. An output stage outputs a signal corresponding to the differential input signal.

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, complimentary transistor, current cource, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor.

Abstract: A clock multiplier circuit is receives an input signal and generates a clock output signal. The clock multiplier circuit generates a number of pulses to be used as the clock output signal, wherein the pulses have a pulsewidth that is independent of the number of pulses generated and independent of the frequency of a clock control signal used for masking. The clock multiplier circuit includes an oscillator, a storage device for synchronization of the masking signal to the pulses and a logic circuit to generate the clock output signal. The clock multiplier circuit causes a number of unmasked pulses to be output as the output clock signal in response to the clock control signal, while other pulses are masked.