Abstract: An electrostatic-discharge/impedance-matching circuit for use in radio frequency (RF) integrated circuits. The electrostatic-discharge/impedance-matching circuit comprises at least one shunt circuit operable to shunt current related to an over-voltage condition and at least one series element operably coupled to the shunt element. The shunt element and series element in combination provide electrostatic discharge protection for the RF signal processing circuit elements on the integrated circuit and also provide a matched input impedance for an incoming RF signal. Various alternate embodiments of the electrostatic-discharge/impedance-matching circuit include first and second shunt elements and a series element operably connected in combination to provide optimal electrostatic discharge protection and impedance matching.

Abstract: A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

Abstract: A signal sensing module senses an RF signal and produces one or more secondary signals representative of the RF signal. An impedance matching control module generates a control signal, based on the one or more secondary signals, which is indicative of an impedance mismatch between a load and a communications device. The control signal is then applied to at least one variable impedance device to adjust the impedance of an impedance matching network and thereby reduce the impedance mismatch between the load and the communications device. In an embodiment, the at least one variable impedance device is a barium strontium titanate, thin film, parallel plate capacitor. In other embodiments, other variable impedance devices such as other types of thin film capacitors or varactor diodes are used to adjust the impedance of the impedance matching network.

Abstract: An apparatus for providing a programmable gain attenuator (PGA) while minimizing the influence of semiconductor switches on the signal being attenuated. An example apparatus comprises a impedance ladder with taps forming the junctions between impedances the PGA is then programmed by grounding the taps through terminating resistors.

Abstract: A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

Abstract: The present invention provides a method for controlling transmission latency in a communications system, wherein the communications system is subject to a noise signal having at least a first noise phase and a second noise phase. The method includes determining a first bit rate for symbols transmitted during the first noise phase, and a second bit rate for symbols transmitted during the second noise phase, the first bit rate and the second bit rate being constrained such that a transmission latency does not exceed a pre-determined maximum allowed transmission latency; and transmitting symbols at the first bit rate during the first noise phase and at the second bit rate during the second noise phase. In other variants, the invention provides an apparatus, a constrained rate reciever, a transmitter and a signal.

Abstract: Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: In one aspect of the present invention, a network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far end data termination devices via a hybrid fiber coaxial network and a cable modem termination system. The described network gateway combines a QAM receiver, a transmitter, a DOCSIS MAC, a CPU, a voice and audio processor, an Ethernet MAC, and a USB controller to provide high performance and robust operation.

Abstract: A novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus. Embodiments of the present invention permit the initiator device to “post” a read request for a specified amount of data from a specified address on the split-transaction bus to an interface that resides between the single-transaction bus and the split-transaction bus. The requested read data is then retrieved over the split-transaction bus and presented in a high-speed memory within the interface for direct access by the initiator device over the single-transaction bus. Latency is avoided because the initiator device is not required to wait for the emergence of the requested read data from the split-transaction bus but, instead, may continue to perform other activities on the single-transaction bus and then obtain the requested read data at a later time.

Abstract: Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making the gate drive of the output driver PMOS and NMOS dependent on the VDD and GND swings. When the VDD or GND increases above normal operating levels, the gate drive of the output driver PMOS is reduced and when the GND or VDD reduces below normal operating levels, the gate drive of the output driver NMOS is reduced. This leads to reduced current flow between the supplies and the pad thereby reducing the VDD and GND bounce problem.

Abstract: A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing.

Abstract: A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain amplifier. The first stage is a transconductance amplifier and the second stage is an operational amplifier. The first stage converts an input signal from a voltage into a current. The second stage converts the current signal to an output voltage signal.

Abstract: A table searching system for facilitating high speed linear searching of a table of information by a plurality of searching agents is provided. The system includes: a memory unit for storing a table of information including a plurality of data entries each having data contents; a plurality of searching agents each being communicatively coupled with the memory unit, and having a port for receiving an associated search key value; and a memory controller unit providing a centralized interface between the memory unit and each of the agents, the controller unit being operative to control the memory unit to provide the contents of a current one of the table entries to each of the agents during each of a plurality of cycles of operation. Each of the searching agents is operative to determine an associated best matching one of the data entries based on comparisons between the associated key value and the contents of the data entries provided by the memory unit.

Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: A data shuffler apparatus shuffles input bits to perform dynamic element matching. The shuffler apparatus includes N input shufflers, each input shuffler having N input terminals and N output terminals, each input terminal of each input shuffler receiving a respective one of the input bits. The apparatus also includes N output shufflers, each output shuffler having N input terminals and N output terminals, the input and output shufflers being interconnected such that each of the N output terminals of each input shuffler is connected to a respective input terminal of a different one of the N output shufflers.

Abstract: A method for communicating information is disclosed wherein a time slot is allocated in a time division multiple access system for a transmission from a subscriber to a headend. Synchronization of a clock of the subscriber with respect to a clock of the headend is enhanced using a message transmitted from the headend to the subscriber which is indicative of an error in a subscriber transmission time with respect to the time slot. A feedback loop process is used to determine at least one of fractional symbol timing correction and carrier phase correction of a transmission from the subscriber to the headend. Filter coefficients are generated at the headend from a ranging signal transmitted from the subscriber to the headend and transmitting the filter coefficients from the headend to the subscriber, the filter coefficients being used by the subscriber to compensate for noise in a transmission from the subscriber to the headend.

Abstract: A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed.

Abstract: A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal, and a reset signal from an I component and a Q component of an FSK modulated signal. The processing continues by generating a delta frequency signal based on the charge signal, the data acquisition signal, and the reset signal. The delta frequency signal is representative of the frequency difference used within the FSK modulation to indicate a logic 1 and a logic 0. The processing then continues by demodulating the delta frequency signal to recapture a stream of data.