Abstract: There is provided a circuit and method for providing a supply voltage to an operational amplifier. A switch has a plurality of inputs connected to a respective plurality of supply voltages. An output of the switch is connected to a supply voltage terminal of an operational amplifier.

Abstract: A network device for monitoring a memory partitioned by an identifier can include at least one port configured to receive at least one packet. The at least one packet includes an identifier relating to priority of the at least one packet. The network device can also include a buffer memory having at least one buffer configured to store the at least one packet, and a counter configured to modify a counter value therein when the buffer memory is accessed with respect to the at least one data packet, wherein the counter corresponds to the identifier with respect to the at least one packet.

Abstract: The present invention provides a delay circuit that may be used to generate delayed signals. The delay circuit comprises a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked loop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked loop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract: A process of maintaining access information between wireless hotspots is disclosed. A logon request from a wireless portable device is received by a first access point of a first wireless hotspot and use of the first access point by the wireless portable device is authenticated to establish an access session. Then, information related to the access session is passed to a shared register accessible by a plurality of wireless hotspots and the access session is monitored to determine whether a disconnect by the wireless portable device occurs. Additionally, when the wireless portable device moves from a coverage area of the first wireless hotspot to one coverage area of one of the plurality of wireless hotspots, the information related to the access session may be used to facilitate access to the one of the plurality of wireless hotspots by the wireless portable device.

Abstract: A process of creating incentives for wireless hotspots by a service provider is disclosed. An access point is provided to a wireless hotspot for wireless devices to wirelessly connect to a larger network in a publicly accessible location. Use of the access point for a portable device is authenticated by requesting submission of an account identifier to the service provider and billing data for a user of the portable device for use of the access point is generated. Use statistics are evaluated of the access point of the wireless hotspot by portables devices and an inducement is provided to the publicly accessible location based on the evaluated use statistics.

Abstract: A wireless network configuration device can include a first communication port configured to access a plurality of nodes positioned in a geographic area, a first storage unit configured to store statistical information from the plurality of nodes with respect to communication between the plurality of nodes and the at least one wireless devices. In addition, the wireless network configuration device can include a processor configured to determine an optimized configuration with respect to the plurality of nodes based on the statistical information, and a second communication port configured to provide data with respect to the optimized configuration to the plurality of nodes, wherein the plurality of nodes are adjusted based on the data.

Abstract: A process of billing for access to and use of a wireless hotspot by a portable device is disclosed. A signal from the wireless hotspot is detected and access to the wireless hotspot is requested. The portable device awaits reply to the access request from the wireless hotspot and supplies account information to an access providing entity. Next, the portable device awaits a billing authorization from the access providing entity and, thereafter, data is exchanged with the wireless hotspot by the portable device when a billing authorized is received from the access providing entity. The account information is used to keep track of charges accrued through the access to and use of the wireless hotspot by the portable device.

Abstract: Embodiments of the present invention perform logical operations utilizing a symmetric logic circuit comprising two logic units. In a symmetric logic circuit, the circuit configuration used to process a first logic input in the first logic unit is the same as the circuit configuration used to process a second logic input in the second logic unit, and the circuit configuration used to process the second logic input in the first logic unit is the same as the circuit configuration used to process the first logic input in the second logic unit. The present invention may be used for logic circuits that perform a variety of logical operations, such as XOR, AND, NAND, OR, or NOR.

Abstract: A feedforward equalizer for equalizing a sequence of signal samples received by a receiver from a remote transmitter. The feedforward equalizer has a gain and is included in the receiver which includes a timing recovery module for setting a sampling phase and, a decoder. The feedforward equalizer comprises a non-adaptive filter and a gain stage. The non-adaptive filter receives the signal samples and produces a filtered signal. The gain stage adjusts the gain of the feedforward equalizer by adjusting the amplitude of the filtered signal. The amplitude of the filtered signal is adjusted so that it fits in the operational range of the decoder. The feedforward equalizer does not affect the sampling phase setting of the timing recovery module of the receiver.

Abstract: A method of switching packets in a network switch includes the step of receiving a packet on a source port of a network switch. Thereafter, the method includes the step of determining whether the network switch has sufficient memory capacity to process the data packet; and if memory capacity is sufficient, then the method reads a selected portion of the packet to determine if the packet is to be sent to a mirrored port. If mirroring is determined, then the method sends the data packet to the mirrored port. The method also includes the step of determining whether the packet is to be sent to a remote CPU for further handling, and sending the data packet to the remote CPU if appropriate. The method additionally includes the step of determining whether the packet is a unicast packet, and if so, placing the packet on an internal communication channel within the network switch for appropriate storing and forwarding.

Abstract: A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus. In one embodiment, an inverter is coupled with a pMOS pass transistor and an nMOS discharge transistor, and the combination is coupled with a data bus. The discharge transistor and pass transistor can be programmed to provide a preselected bus operational characteristics. In another embodiment, multiple nMOS discharge transistors can be coupled to the data bus via the pass transistor, with each of the discharge transistors being selectively programmed to provide additional preselected bus operational characteristics, multiple, programmable discharge transistors, thus selectably imposing encoded and multilevel logic signals on the data bus. In another embodiment, a bidirectional data transfer bus circuit couples two data busses while imposing a limited, controlled voltage swing during the transfer.

Abstract: A one time programmable memory circuit includes a one time programmable memory array. A write circuit outputs data to the one time programmable memory array. A power up write controller outputs the data and a write enable signal to the write circuit. A read circuit outputs data from the one time programmable memory array upon a read enable signal received from a read controller. An address decoder communicates with the power up write controller and the read controller, for providing an address to the one time programmable memory array.

Abstract: A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.

Abstract: An on-chip multiple tap transformed balun includes a 1st winding and a 2nd winding having two portions. The 1st winding is on a 1st layer of an integrated circuit and is operably coupled for a single ended signal. The 1st and 2nd portions of the 2nd winding are on a 2nd layer of the integrated circuit. The 1st portion of the 2nd winding includes a 1st node, a 2nd node, and a tap. The 1st node is operably coupled to receive a 1st leg of a 1st differential signal and the 2nd node is coupled to a reference potential. The tap of the 1st portion is operably coupled for a 1st leg of a 2nd differential signal. The 2nd portion of the 2nd winding includes a 1st node, 2nd node, and tap. The 1st node is operably coupled to receive a 2nd leg of the 1st differential signal and the 2nd node is operably coupled to the reference potential. The tap of the 2nd portion is coupled for a 2nd leg of the 2nd differential signal.

Abstract: A network switch for network communications includes a first data port interface, wherein the first data port interface supports a plurality of data ports for transmitting and receiving data at a first data rate. The network switch also includes a second data port interface, wherein the second data port interface supports a plurality of data ports for transmitting and receiving data at a second data rate, along with a third data port interface for transmitting and receiving data at a third data rate. A CPU interface is provided and configured to communicate with a CPU. The switch includes a first internal memory communicating with the first data port interface, the second data port interface, and the third data port interface. A first memory management unit having an external memory interface for communicating data from at least one of the first data port interfaces and the second data port interface to and from an external memory is also provided.

Abstract: A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a separate reset signal or signals. The arbiters are concurrently released from reset when the first reset signal is deasserted, and may have a consistent reset state to provide for synchronization of the arbiters. The agents may be independently released from reset by the separate reset signals. Accordingly, the arbiters may be synchronized and may remain synchronized even if the corresponding agents are released from reset at different times, or are temporarily held in reset for any reason.

Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

Abstract: A process of handling packet data in a packet buffer is disclosed. Free pointers are stored in a plurality of free pointer queues, with each of the plurality free pointer queues in a form of a linked list and the free pointers are retrieved from each of the plurality of free pointer queues and storing in a prefetch memory to provide a throughput of one free pointer per clock cycle. When an initial portion of a data packet is received, two free pointers are retrieved from the prefetch memory. One of the two free pointers is stored in a start pointer register connoting a start of the data packet and one free pointer is supplied for data elements of the data packet. One free pointer per middle data element is supplied, while no new pointer is needed for the end of packet data element.

Abstract: A method and circuit for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.

Abstract: A line driver selectively drives one of two transmission lines. The line driver includes a differential amplifier connected to first and second differential switches. The first differential switch is connected between an output of the differential amplifier and a first of two transmission lines. The second differential switch is connected to the output of the differential amplifier and to the second of two transmission lines. The first and second differential switches are controlled by respective first and second control signals. The output of the differential amplifier is connected to either the first or the second transmission line in response to the first and second control signals. The differential switches include loopback protection to an prevent an incoming signal from passing from one transmission line to another during power down mode.