Abstract: Existing (already installed) plain old telephone service (POTS) wiring at a customer premises is used as the wiring infrastructure for a local area network and additionally continues to provide ordinary POTS services at the customer premises. The network signals associated with the local area network and the POTS signals delivering POTS services coexist on the POTS wiring at the customer premises using frequency division multiplexing. In additional to POTS service, the subscriber loop also provides access to xDSL (digital subscriber line) signals associated with a wide area network (WAN). Thus three distinct networks (the PSTN associated with POTS, xDSL and the LAN)) coexist on a single wiring infrastructure.

Abstract: Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. The separate timing recovery loops can be used to compensate for timing phase errors in the clock generation circuit that are different for each path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. The separate AGC loops can be used to compensate for gain errors on a path-by-path basis.

Abstract: A cable modem system and method is provided for supporting data transfer protocols that extend beyond standard protocols used in conventional data over cable systems. A cable modem in accordance with the invention determines, during registration, whether a CMTS with which it communicates is capable of supporting an extended protocol, and if it is, transfers data to the CMTS in accordance with the extended protocol. Additionally, a CMTS in accordance with the invention is notified during registration whether or not a cable modem supports an extended protocol and stores this information. When a request for transmission opportunity is subsequently received from the cable modem, the CMTS accesses the stored information to determine if the cable modem supports the extended protocol. If the cable modem supports the extended protocol, the CMTS processes data received from the cable modem during the transmission opportunity in accordance with that protocol.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. An IC die is mounted to the first substrate surface. A plurality of solder balls is attached to the second substrate surface. A thermal connector is mounted to the second substrate surface. The thermal connector is configured be coupled to a printed circuit board.

Abstract: A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.

Abstract: A method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.

Abstract: A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, allowing access to a memory cell at least twice during the memory access period, thereby providing dual-port functionality. A WRITE-AFTER-READ operation without a separate, interposed PRECHARGE cycle, is completed within one memory access cycle of the hierarchical memory structure. The method includes locally selecting the first memory location of a first datum; locally sensing the first datum (i.e.

Abstract: Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fC=fS4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fS is correct, and will be shifted in one direction or the other if the sampling frequency fS is too high or too low.

Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is interpolated by N and processed by a digital filter to obtain the pulse shape required by the particular communication application. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. When implemented in such manner, the logical implementation and memory replaces digital filtering circuits, DAC decoding logic circuit and re-synchronization logic circuits that are conventionally implemented in hardware. Thus, the hardware functionality of these circuits is rendered into arithmetic form and implemented in a memory device.

Abstract: A design for a differential amplifier with a large input common mode signal range. The differential amplifier comprises two differential pairs, each having two amplifying MOSFETs. A source follower is connected to the gate terminal of each amplifying MOSFET in one of the differential pairs. A differential signal applied to the differential amplifier comprises two separate signal. Each separate signal is applied to the gate terminals of both the amplifying MOSFET in the differential pair not driven by the source follower and the driven MOSFET of the source follower. The differential amplifier further comprises a pair of switch MOSFETs connected to a current source MOSFET. The switch MOSFETs act to control the distribution of the total current flowing from the current source MOSFET and, consequently, to determine which differential pair works dominantly to amplify the input signals.

Abstract: Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. The chip architecture enables a degree of parallel processing of authentication and encryption/decryption functions achieved by an alignment logic configuration that distinguishes portions of a non-pre-padded network security protocol (e.g., SSL (v3) or TLS) packet requiring one and/or another operation (authentication and/or encryption) to permit single pass processing of non-pre-padded network security protocol data. In some embodiments, processing efficiency may be further enhanced by the pipelining of successive packets to be processed.

Abstract: High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.

Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop for minimizing averaging errors at the strip ends.

Abstract: The drift between a write pointer and a read pointer processing packets of data through a FIFO buffer is compensated for by adjusting the start of the read pointer relative to the write pointer. The FIFO buffer is sized to include a number of storage cells equal to the product of the maximum frequency offset between the write clock and read clock and the maximum number of data units in a packet. Initially the start of the read pointer is delayed, relative to the write pointer, by a portion of the number of storage cells in the FIFO. During the processing of a data packet it is determined whether the read pointer is drifting toward or away from the write pointer. If the read pointer is drifting away from the write pointer, for subsequent data packets, the read pointer is started almost immediately after the write pointer writes to the first storage cell in the FIFO.

Abstract: A system for performing a computationally efficient method of searching through N Vector Quantization (VQ) codevectors for a preferred one of the N VQ codevectors predicts a speech signal to derive a residual signal, derives a ZERO-INPUT response error vector common to each of the N VQ codevectors, derives N ZERO-STATE response error vectors each based on a corresponding one of the N VQ codevectors, and selects the preferred one of the N VQ codevectors based on the N ZERO-STATE response error vectors and the ZERO-INPUT response error vector.

Abstract: A method and computer program product for recognizing and optimizing the transmission of TCP/IP style traffic across a DOCSIS network. According to the method of the present invention, a full TCP protocol packet is initially transmitted across a DOCSIS network to be learned by the CMTS. Redundant fields in the TCP protocol packet are entirely suppressed when subsequent TCP protocol packets are transmitted across the DOCSIS network. Non-redundant fields in the TCP protocol packet are delta-encoded using a delta-encoded value when subsequent TCP protocol packets are transmitted. The delta-encoded values represent the change in value of the current TCP packet from the previous TCP packet for a non-redundant field. This enables the CMTS to provide an exact reconstruction of all subsequently transmitted compressed TCP protocol packets.

Abstract: An oscillator circuit is disclosed which includes an oscillator to generate a first signal having a first frequency, a second oscillation source to generate a second signal having a second frequency, the second oscillator comprising a frequency divider coupled to the oscillator, and a mixer to mix to the first and second signals, wherein the oscillator, frequency divider and mixer are each quadrature. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A method of searching a plurality of Vector Quantization (VQ) codevectors for a preferred one of the VQ codevectors to be used as an output of a vector quantizer for encoding a speech signal, includes determining a quantized prediction residual vector, and calculating a corresponding unquantized prediction residual vector and the energy of the difference between these two vectors (that is, a VQ error vector).

Abstract: There is provided a circuit and method for providing a supply voltage to an operational amplifier. A switch has a plurality of inputs connected to a respective plurality of supply voltages. An output of the switch is connected to a supply voltage terminal of an operational amplifier. The input of the switch is selected in dependence of the voltage levels to which a signal is to be amplified.

Abstract: Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of the present invention attempt to maintain the proper current ratio between reference and output supplies by adjusting the reference output of the current mirror. An existing reference voltage on the output side of the mirror can be used or a reference voltage can be created to be used for the voltage regulation of the reference side of the current mirror.