Abstract: An active termination for a transmission line comprising a reference impedance, a terminating impedance and a control circuit. The reference and terminating impedances are identical circuits made on the same integrated circuit in close proximity to one another. Both impedances are made of an active and a passive resistor in series. The active resistor is a CMOS transistor operated as a voltage controlled resistor. A control circuit senses the impedance of the reference impedance and generates a control signal to change the impedance of the reference and terminating impedances such that they are made equal to the impedance of the transmission line. An alternate embodiment of the invention comprises an active resistor and a passive resistor in series to form a terminating impedance network. A control circuit senses the voltage on the transmission line and adjusts the active resistor to terminate the transmission line with the correct value of resistance.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in accordance with a corresponding one of the sampling clock signals. For each of the sampling clock signals, a phase error is generated from a corresponding phase detector. The phase errors are filtered by a set of corresponding loop filters. The filtered phase errors are provided to a set of corresponding oscillators to generate phase control signals. The phase control signals are provided to a set of corresponding phase selectors to generate the sampling clock signals.

Abstract: A system and method are presented for changing physical layer (PHY) parameters in a PHY device of a communications system. New parameters are written to a first-in first-out queue in a serial interface, while the scheduled time for the changeover is written to a control register in the serial interface. When the time for the changeover occurs, the parameters are written to the PHY device via a port of the serial interface.

Abstract: A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a MOSFET and applying this replicated voltage to the body terminal. In this manner, the effect of the body transconductance, at high frequencies, becomes a function of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the transistor. At high frequencies, the biasing scheme mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET by contributing a negative half plane zero to the transfer function of the feedback network, and reduces the power consumed by the gain boosting amplifier.

Abstract: A data switch for network communications includes at least one first data port interface which supports a plurality of data ports which transmit and receive data at a first data rate. At least one second data port interface is provided; the at least one second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the at least one first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory.

Abstract: Gain scaling of multistage, multi-bit delta sigma modulators for higher signal-to-noise ratios. In a multistage delta sigma modulator having a modulator stage with an integrator, a multi-bit quantizer, and a multi-bit digital-to-analog converter, the multi-bit quantizer is companded to cause a feedback signal, produced by the multi-bit digital-to-analog converter, to have a first gain, with respect to an integrated signal received by the multi-bit quantizer, set greater than one. A second gain, of the integrator, is reduced so that an overall gain of the modulator stage remains equal to one. A third gain, of a stability correction gain element connected to an input of the modulator stage, is increased so that a swing of the integrated signal remains within a dynamic range of an operational amplifier used to implement the integrator, and the multistage delta sigma modulator can realize the higher signal-to-noise ratio.

Abstract: A system and method for guaranteeing a delay jitter bound when scheduling bandwidth grants for voice calls via a communication medium is provided. The method includes the steps of: determining the delay jitter bound; based on the determined delay jitter bound, dividing a packetization frame period into phases; assigning a voice call to one of the phases; and scheduling a bandwidth grant to the voice call during the assigned phase, thereby guaranteeing the delay jitter bound. The system includes a scheduler, where the scheduler determines the delay jitter bound, divides a packetization frame period into phases based on the determined delay jitter bound, assigns a voice call to one of the phases, and schedules a bandwidth grant to the voice call during the assigned phase, thereby guaranteeing the delay jitter bound. A dejitter buffer implements a way to provide zero jitter service, even though the packet transmission on the cable network has jitter, by delaying the packet and thus converting jitter into delay.

Abstract: A method and system for creating an ethernet-formatted packet from an upstream DOCSIS packet. The upstream packet is first received along with packet characteristic data that is contained in physical layer prepend data and in the packet header. A packet tag is then created, based on the packet characteristic data. The packet characteristic data includes identifiers for the transmitting remote device and the channel over which the transmission is sent. Packet characteristic data also includes information about the physical characteristics of the transmission signal, such as the power level and time offset. The packet characteristic data also includes administrative information, such as the minislot count at which the packet is received and whether the packet was received in contention. The packet tag is appended to the payload of the upstream packet. Also appended to the payload is an encapsulation tag, and source and destination address headers. The result is a packet in an ethernet format.

Abstract: Clock signals and digital data signals at a variable frequency are introduced to the input of a FIFO and are passed from the FIFO at a second (or intermediate) frequency controlled by a numerically controlled oscillator. To regulate the frequency of the signals from the numerically controlled oscillator, the phases of the clock signals at the variable frequency are compared in a phase detector with the phases of the signals from the numerically controlled oscillator to generate an error signal. The error signals and the signals at a fixed sampling frequency higher than the intermediate frequency regulate the frequency of the signals from the numerically controlled oscillator and thus the frequency of the digital data signals from the FIFO. The digital data signals from the FIFO are converted to a pair of signals at the second frequency.

Abstract: A queue length arbiter system provides for selecting from a plurality of N queues requiring access to a resource. The system includes: an arbitration circuit; and a plurality of weight circuits each being associated with a corresponding one of the queues, and being operative to store a corresponding weight count value, and also being operative to initialize the corresponding weight count value to a corresponding initial weight value determined based on a length value indicative of a number of data portions enqueued at the corresponding queue at an initial time, and being further operative to decrease the corresponding weight count value in response to a corresponding one of a plurality of grant signals, and also being operative to generate a corresponding one of a plurality of weight count signals, the corresponding weight count signal carrying the corresponding weight count value.

Abstract: A circuit and method for obtaining a stable delay for a clock signal comprises a current source to generate a constant current having a first value; first and second current over capacitance (I/C) stages coupled to the current source and between a supply voltage and ground; and a capacitor, having a second value and coupled to a node formed by an output of the first I/C stage and an input of the second I/C stage. Application of a clock signal to an input of the first I/C stage produces an output at a logic gate coupled to an output of the second I/C stage. The output has a stable delay based on the first and second values. Additionally, the first and second values (i.e., the value of the current or capacitance) can be changed to achieve a desired amount of the delay applied to the input clock signal.

Abstract: A super set of space-time block codes is combined with set partitioning to form super-orthogonal space-time trellis codes having full diversity, enhanced coding gains, and improved rates. In communications systems, these codes are implemented by an encoder of a diverse transmitter to send an information signal to a receiver having one or more receiver elements. A decoder in the receiver decodes the encoded signal to reproduce the information signal. A method of the invention is used to generate set partitioning structures and trellis structures that enable code designers to systematically design the codes of the invention.

Abstract: A signal coupler is provided which decreases the number of discreet elements required to provide low pass filtering for the plain old telephone service (POTS). The low pass filtering is shifted to areas of the signal coupler circuit which do not operate with the high battery voltage present on telephone lines The low voltage filtering reduces the need for components which are capable of operating in the high voltage environment and therefore reduces the space on the circuit board which is occupied by each of the signal couplers. In this way, the number of individual subscriber lines that a given circuit board can accommodate can be increased.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus. In one embodiment, an inverter is coupled with a pMOS pass transistor and an nMOS discharge transistor, and the combination is coupled with a data bus. The discharge transistor and pass transistor can be programmed to provide a preselected bus operational characteristics. In another embodiment, multiple nMOS discharge transistors can be coupled to the data bus via the pass transistor, with each of the discharge transistors being selectively programmed to provide additional preselected bus operational characteristics, multiple, programmable discharge transistors, thus selectably imposing encoded and multilevel logic signals on the data bus. In another embodiment, a bidirectional data transfer bus circuit couples two data busses while imposing a limited, controlled voltage swing during the transfer.

Abstract: A constant impedance filter maintains a constant input impedance for frequencies that are both inside the filter passband and outside the filter passband. The constant input impedance appears as a pure resistance. The constant impedance filter includes a plurality of filter poles that are connected in series. Each of the filter poles include an inductor, a capacitor, and a resistor. The value of the inductor, the capacitor, and the resistor are selected to provide a constant input impedance over frequency for each pole of the filter, which produces a constant input impedance for the entire filter over frequency. The constant impedance filter can be implemented as a low pass filter, a high pass filter, or a bandpass filter. Furthermore, the constant impedance filter can be implemented in a single-ended configuration or a differential configuration.

Abstract: A limited swing driver with a pass transistor coupled between a memory cell and an associated bitline; an inverter, its output coupled to the gate of the pass transistor, and its input coupled with the memory cell. A memory node is formed at the juncture of the inverter input and the memory cell forming a memory node. The driver also includes a discharge transistor coupled between the memory node and ground. The discharge transistor is driven by an input on the discharge transistor gate. It is preferred that the discharge transistor being programmed to produce a limited swing voltage at the memory node. It is desirable that the limited swing voltage be less than about 350 mV, and it is preferable that the limited swing voltage be between about 300 mV and about 200 mV.

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.