Abstract: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.

Abstract: To help eliminate overlapping cell placements or to reduce routing congestion in an IC layout wherein cells are integer multiples of a standard size cell unit, the layout is organized into an array of rectangular blocks, each having capacity to accommodate several cell units. A separate equation is established for each block relating a sum of a set of flow variables to an “overflow factor”. Each flow variable of the equation for each block corresponds to a separate one of that block's neighboring blocks and represents an estimated number of cell units that must be moved to or received from the corresponding neighboring block to eliminate overlapping cell placements or routing congestion within the block. The overflow factor for each block represents an estimated total number of cell units the block must pass into its neighboring blocks or an estimated maximum number of cell units it may receive from its neighboring blocks in order to eliminate cell overlap or routing congestion in all blocks.

Abstract: A circuit and method for driving the output signal, having a common-mode voltage and an output swing, of an integrated circuit. In accordance with an aspect of an embodiment of the present invention, a first power supply provides the termination voltage for the output signal and a second power supply provides the power to set the common mode voltage. In accordance with another aspect, the common-mode voltage and the output swing are programmable.

Abstract: The present invention presents optimization methods for interconnect geometries that readily extend to the UDSM region for determining on-chip interconnect process parameters more realistically and accurately than in the prior art. A method for reconstruction flow that re-assembles each of a number of optimized structures into one optimized interconnect process file, such as a process technology file for extractors. This optimized process technology file can use not only extracted interconnect process parameters but also the input of LPE (Layout Parasitic Extraction) tools in physical verification stage.

Abstract: An assertion based transaction recording method is used to represent a signal-level transaction having a prefix and a suffix as an abstract transaction. The method models the signal-level transaction as an assertion requiring that the transaction suffix must occur following any occurrence of the transaction prefix. A finite-state-machine (FSM) implementation of the assertion records a tentative abstract transaction upon recognizing the first condition of the prefix. If the FSM recognizes that the prefix cannot complete, it cancels, or deletes, the tentative abstract transaction record. The implementation can track multiple tentative abstract transaction records that may co-exist prior to completion of the transaction prefix. Upon recognizing that the transaction prefix corresponding to the start point of the tentative abstract transaction has completed, the tentative abstract transaction record is committed.

Abstract: A method is defined which reduces the number of applied test patterns while maintaining identical fault coverage for a given set of weighted random patterns. Reduction is accomplished by simulating the weight sets in reverse order against a full (untested) fault list but allowing fault mark-off for initially effective patterns only (patterns which detected faults). This results in some patterns which initially detected only a few faults (due to their exposure to a small untested fault list) to detect a greater number of faults (due to their exposure to a full fault list), while other patterns which were initially effective become ineffective (detected no faults). Since the same faults are still detected there is no loss of coverage. Only those patterns which remain effective after exercising the reverse simulation are ultimately applied on the tester.

Abstract: One embodiment of the invention is a recursive partitioning method that place circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots) for a net in the region, the method then identifies the set of sub-regions (i.e., the set slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.

Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.

Abstract: A technique for constructing a balanced H-Tree clock layout suited for application to clock signals in integrated circuits, but applicable to other signals requiring balanced distribution over a wide area, involves routing clock wires in a circuit design wherein internal circuit blocks are divided, to the extent possible, into groups having an equal number of circuit blocks. An upper H-Tree clock layout structure is established using the center of mass of each of the circuit block groups as guideposts. Adjustments in wire length to balance the wires of the H-Tree layout. A lower H-Tree clock layout structure is established using center points between pairs of adjacent or nearby circuit blocks as guideposts for the endpoints of clock wires, and then routing, to the extent necessary, wire segments to the individual circuit blocks.

Abstract: An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodic steady state response; 2) solving the non-linear system via a Newton iterative method, where each iteration of the Newton method involves solution of a respective linear system of equations; and 3) for each iteration of the Newton method, solving the respective linear system of equations associated with the iteration of the Newton method via an iterative technique. The iterative technique may be a matrix-implicit application of a Krylov subspace technique, resulting in a computational cost that grows approximately in a linear fashion with the number of nodes in the circuit.

Abstract: A method and apparatus for the synthesis of electronic circuits is described herein. More particularly, the system supports the synthesis of both analog-only, and mixed digital/analog circuitry. The circuit designers knowledge is reused to effect the simulation of mixed analog and digital circuitry, determining data points and curve-fitting the data points to determine a model that closely approximates the simulated circuit performance. The model describes the parameterization of circuit features with respect to circuit performance. The parameterization is used to develop a behavioral model of the circuit that does not retain any of the physical description of the circuit.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e.g., an IEEE standard 1149.1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A system and method for protecting circuit designs from unauthorized use involves techniques for watermarking by embedding a hidden, recognizable input/output signature or code into the circuit design. An internal sequential function, such as a finite state machine, within the circuit design is used to generate a predictable output sequence when a known input sequence is applied. The free input configurations in the internal sequential function of the circuit design are identified and modified to generate the desired output sequence when the known input sequence is applied. A path among the free input configurations is selected, with output values in the desired output sequence being assigned the various state transitions. If there are not enough free input configurations to meet specified watermarking robustness criteria, then additional free input configurations may be added by, for example, adding one or more inputs, outputs or states to the finite state machine.

Abstract: The mechanism is directed towards method and apparatus for representing multidimensional data. Some embodiments of the invention provide a two-layered data structure to store multidimensional data tuples that are defined in a multidimensional data space. These embodiments initially divide the multidimensional data space into a number of data regions, and create a data structure to represent this division. For each data region, these embodiments then create a hierarchical data structure to store the data tuples within each region. In some of these embodiments, the multidimensional data tuples are spatial data tuples that represent spatial or geometric objects, such as points, lines, polygons, regions, surfaces, volumes, etc. For instance, some embodiments use the two-layered data structure of the invention to store data relating to geometric objects (such as rectangles) that represent interconnect lines of an IC in an IC design layout.

Abstract: A feasible floorplan of a circuit is determined and budgeted in the early phases of circuit design. The process of determining the floorplan and budget includes estimating RTL complexity, physical partitioning, block placement, block i/o placement and top level global routing, and verifying feasibility of the floorplan. Allocation of global timing constraints to each block is performed by producing logic cones representing timing of circuit paths in each block. The circuit paths are optimized to determine a feasible timing for each block. The global constraints are allocated proportionally to each block based on the feasible timing for each block.

Abstract: A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.

Abstract: Some embodiments of the invention provide a method that identifies a set of routes for a net that has a set of pins in a region of a design layout. The method initially partitions the region into a number of sub-regions. It then identifies a first set of sub-regions that contains the net's pins. The method next determines whether a storage structure stores a set of routes for the identified first set of sub-regions. If so, the method retrieves the set of routes. If not, the method generates a set of routes. In some embodiments, the method generates a set of routes by first identifying a connection set of sub-regions that when combined with the first set forms a closed set of sub-regions. The closed set of sub-regions does not have any sub-region that is not adjacent to another sub-region in the closed set. The storage structure stores a set of routes for the closed set.

Abstract: A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described. With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences so that when they are applied, all outputs of embedded RAMs attain known values.