Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
  • Method and device for determining fail bit repair solution, and chip
    Patent number: 11862272
    Abstract: A local region to be repaired including the fail bit is determined. A preliminary repair LR circuit for repairing the local region to be repaired is determined (S210). A region level of the local region to be repaired is determined (S230) according to the number of available GR circuits other than any replacement GR circuit configured for replacing the preliminary repair LR circuit and the number of available LR circuits. It is controlled, according to the region level of the local region to be repaired, to repair the fail bit by the GR circuit or the LR circuit (S240).
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yui-Lang Chen
  • Sense amplifier, memory and data readout method
    Patent number: 11862284
    Abstract: The present disclosure provides a sense amplifier, a memory, and a data readout method, and relates to the field of semiconductor memory technologies. The sense amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first switch, a second switch, a third switch, and a fourth switch. During the offset compensation stage of the sense amplifier, the switching states of the first switch to the fourth switch are controlled so that the first NMOS transistor and the second NMOS transistor are configured to be in a cross-coupled amplification mode, and the first PMOS transistor and the second PMOS transistor are configured to be in a diode connection mode. The present disclosure enables to realize the offset compensation of the sense amplifier and improves the correctness of data readout by the memory.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kanyu Cao, Sungsoo Chi, WeiBing Shang, Ying Wang
  • Power supply circuit and memory
    Patent number: 11862228
    Abstract: A power supply circuit and a memory are provided. The power supply circuit includes a voltage source, multiple power supply circuits and a control circuit. The multiple power supply circuits are connected to the voltage source. If the voltage source is effective and the multiple power supply circuits are in an enable state, a voltage of a power supply terminal is pulled up to a preset voltage, and power is supplied to the load units during the pulling up process. A first-type power circuit enters the enable state if a first enable signal is received, and each of second-type power supply circuits enters the enable state if second enable signal is received.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES INC.
    Inventor: Rumin Ji
  • Method for manufacturing semiconductor structure with core and peripheral regions and semiconductor structure thereof
    Patent number: 11864373
    Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following operations. A substrate is provided, includes a core region and a peripheral region. A preset barrier layer is formed on the substrate, and covers the core region and the peripheral region. At least a part of the preset barrier layer corresponding to the peripheral region is removed to expose a part of the substrate, and to take a reserved part of the preset barrier layer as a first barrier layer. A dielectric layer and a first conductive layer are successively formed on the first barrier layer and the substrate. A part of the dielectric layer and the first conductive layer on the first barrier layer are removed, to reserve a part of the dielectric layer and the first conductive layer on the first barrier layer closer to the peripheral region.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengmeng Yang, Jie Bai
  • Data transmission circuit and method, and storage apparatus
    Patent number: 11862286
    Abstract: A data transmission circuit includes: a comparison circuit, configured to compare received first data on a data bus with received second data on a global data line and output a comparison result of whether a number of different bits between the first data and the second data exceeds a preset threshold; a data conversion circuit, configured to: if the comparison result indicates that the number of different bits exceeds the preset threshold, invert the first data and transmit the inverted first data to the global data line, and otherwise, transmit the first data to the global data line; and a read-write conversion circuit, configured to: if the comparison result indicates that the number of different bits exceeds the preset threshold, transmit data on the global data line to a complementary local data line, and otherwise, transmit data on the global data line to a local data line.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Liang Zhang
  • Method for evaluating hot carrier injection effect of device
    Patent number: 11860220
    Abstract: A method for evaluating a Hot Carrier Injection (HCI) effect of a device is provided. The method includes, a ratio of a substrate current to a drain current of a first device at different gate-source voltages is acquired, and recorded as a first current ratio; a ratio of a substrate current to a drain current of a second device at different gate-source voltages is acquired, and recorded as a second current ratio, the second device is subjected to process parameter adjustment or device parameter adjustment relative to the first device; and an influence of the process parameter adjustment or the device parameter adjustment on an HCI effect of the device is determined based on the second current ratio and the first current ratio.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC
    Inventor: QiAn Xu
  • Memory and method for writing memory
    Patent number: 11862237
    Abstract: A memory includes a bank, the bank includes a plurality of sections, each of the plurality of section includes a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, and each of the plurality of storage units is connected to one of the plurality of word lines and one of the plurality of bit lines; the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Tianchen Lu
  • Reading and writing method of memory device and memory device
    Patent number: 11862229
    Abstract: A reading and writing method for a memory device and a memory device are provided. The memory device includes a memory chip. The reading and writing method of the memory device includes that: during operation of the memory chip, the temperature of the memory chip is measured, and a writing recovery time of the memory chip is adjusted according to the temperature.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Monitor wafer measuring method and measuring apparatus
    Patent number: 11862495
    Abstract: The present invention relates to a monitor wafer measuring method and measuring apparatus. The monitor wafer measuring method comprises the following steps: fixing a product wafer, the product wafer having several alignment marks and product measuring sites corresponding respectively to the alignment marks; determining the product measuring sites according to the alignment marks; and placing a monitor wafer, a projection of the monitor wafer in a vertical direction being aligned with and coinciding with the product wafer. The present application can reduce or even eliminate positional errors of the monitor wafer during a measurement process, such that product-level measuring position accuracy can be achieved for the monitor wafer and further, the measuring machine itself and process changes can be monitored in a better way.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: He Zhu
  • Method for manufacturing semiconductor structure and semiconductor structure
    Patent number: 11864371
    Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate having a first surface and a second surface opposite to each other, and a transistor being arranged on the second surface; forming release holes in the substrate, the release holes extending into the transistors, bottoms of the release holes being located in channel regions of the transistors, and top surfaces of the release holes being flush with the first surface; and forming a conductive structure in the release holes.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shuai Guo
  • Semiconductor structure and method for manufacturing same
    Patent number: 11864377
    Abstract: A semiconductor structure includes: a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on a surface of the first conductive layer away from the substrate, and third conductive layers covering side walls of the first conductive layer and in contact with the second conductive layer. Contact resistance between the third conductive layers and the second conductive layer is less than contact resistance between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Cheng Liu
  • Memory test method and memory test apparatus
    Patent number: 11862276
    Abstract: The present application relates to the technical field of integrated circuits, and in particular, to a memory test method and a memory test apparatus. The memory test method includes: providing a to-be-tested memory, where the to-be-tested memory includes a plurality of memory cells; alternately writing a first write value and a second write value into a memory cell of the memory cells at a preset frequency; writing a test write value into the memory cell; judging whether a data read from the memory cell is the test write value, and determining that a capacitance-frequency characteristic of the memory cell is abnormal if the data is not the test write value. According to the present application, the capacitance-frequency characteristic of the to-be-tested memory is accurately tested, to improve the field of memory products.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Wei Huang, Chi-Shian Wu
  • Wafer breaking method and chip failure analysis method
    Patent number: 11860073
    Abstract: Embodiments of the present disclosure relate to a wafer breaking method and a chip failure analysis method. The wafer breaking method includes: providing a wafer sample, which includes a first surface with a target point and a second surface opposite to the first surface; forming a first crack and a second crack, orthographic projection of which on the first surface are on the same straight line as the target point in a preset direction; forming a cutting slot, there is a preset distance between a bottom of the cutting slot and the first surface, and orthographic projection of the first crack and the second crack are on the same straight line as the cutting slot; and breaking the wafer sample along the cutting slot, such that the wafer sample is broken in the preset direction to obtain a cross section of the target point in the preset direction.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Wen-Lon Gu
  • Comparison circuit and memory
    Patent number: 11862225
    Abstract: A comparison circuit includes a reference adjustment module, a signal receiving module, and a control module. The reference adjustment module is configured to receive a first reference signal and output a second reference signal. The reference adjustment module is further configured to receive an adjustment signal, and unidirectionally adjust the equivalent coefficient within a preset value interval when the adjustment signal is received. The signal receiving module is configured to receive the second reference signal and an external signal. The control module is configured to: receive an enable signal and the comparison signal; and during a period of continuously receiving the enable signal, when the comparison signal jumps, terminate the output of the adjustment signal.
    Type: Grant
    Filed: April 24, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zhiqiang Zhang
  • Test circuits and semiconductor test methods
    Patent number: 11860217
    Abstract: The present application relates to a test circuit, comprising: M stages of test units, first terminals of test units in each stage being all connected to a power wire, second terminals of test units in each stage being all connected to a ground wire, third terminals of test units in the first stage being connected to the power wire, and third terminals of test units in the ith stage being connected to fourth terminals of test units in the (i?1)th stage; wherein, the M and i are positive integers greater than or equal to 2.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: ChihCheng Liu
  • Test method for control chip and related device
    Patent number: 11862268
    Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chuanqi Shi, Heng-Chia Chang, Li Ding, Jie Liu, Jun He, Zhan Ying
  • Manufacturing method of semiconductor structure
    Patent number: 11862513
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A substrate is provided. A barrier layer is formed on the substrate. A sacrificial layer is formed on the barrier layer. An opening pattern is formed over the sacrificial layer by utilizing a photolithography process. The sacrificial layer is etched according to the opening pattern to form first trenches by using the barrier layer as an etch stop layer. A medium layer material is filled in the first trenches. The sacrificial layer is etched to form second trenches by using the barrier layer as the etch stop layer. A hard mask layer material is filled in the second trenches. The medium layer material is etched to form a hard mask layer by using the barrier layer as the etch stop layer.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xifei Bao
  • Electrostatic discharge protection circuit
    Patent number: 11862965
    Abstract: The present disclosure provides an electrostatic discharge protection circuit, a chip including a first pad and a second pad. The electrostatic discharge protection circuit includes a trigger unit and a discharge transistor. The trigger unit is connected between the first pad and the second pad, provided with a trigger terminal, and configured to generate a trigger signal when there is an electrostatic pulse on the first pad. The first pad is connected to a first voltage, the second pad is connected to a second voltage, and the first voltage is greater than the second voltage. The discharge transistor has a first terminal connected to the first pad, and a second terminal connected to the second pad, and discharges an electrostatic charge to the second pad when triggered by the trigger signal.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qi'an Xu
  • Sense amplifier, storage device and read-write method
    Patent number: 11862283
    Abstract: A sense amplifier includes a first switch unit, a second switch unit, and an amplifier-latch module. A first port of the amplifier-latch module is electrically connected, via the first switch unit, to a bit line connected with a storage unit, and a second port of the amplifier-latch module is electrically connected to a reference voltage signal via the second switch unit. The amplifier-latch module is configured to amplify a signal in a sensing amplification phase. The first switch unit is configured to transmit a voltage on the bit line to the first port before the sensing amplification phase. The second switch unit is configured to transmit the reference voltage signal to the second port before the sensing amplification phase, and disconnect an electrical connection between the reference voltage signal and the second port in the sensing amplification phase.
    Type: Grant
    Filed: August 22, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Ying Wang, Sunsoo Chi
  • Voltage conversion circuit
    Patent number: 11863179
    Abstract: A voltage conversion circuit is provided. The circuit includes a first input module and a second input module. The first input module is connected to a first voltage and has a first input terminal for receiving an input signal and outputting a conversion signal, a high level of the input signal is a second voltage which is less than the first voltage; The second input module is connected to the first input module and has a second input terminal and an output terminal, the second input terminal is configured to receive a sampling signal, and the second input module is configured to sample the conversion signal according to the sampling signal and output an output signal via the output terminal.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kangling Ji