Abstract: A testing method for a packaged chip includes: acquiring a target chip; in the post-burn-in test process, testing a first data retention time of each memory unit on the target chip; comparing the first data retention time of each memory unit with a preset reference time; and, determining that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time. In the present application, by testing the first data retention time of each memory unit on the target chip in the post-burn-in test process, it is determined that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: The present disclosure relates to a memory test system and a memory test method. The memory test system comprises: a plurality of test devices, a host computer, and driving modules. Each of the test devices is provided with a test interface used for connecting a memory to be tested. The host computer is respectively connected to the plurality of test devices and configured to control the test devices to test the memory to be tested. The driving modules are connected to the test devices and configured to output, to the test devices, driving signals used for driving the test devices to perform data interaction with the host computer.

Abstract: The present disclosure discloses a semiconductor device and a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes following steps: providing a semiconductor substrate, and forming active regions and trench isolation structures in the semiconductor substrate, wherein the trench isolation structures are located between the active regions; forming first grooves in the active regions; filling the first grooves to form inversion polysilicon layers, the inversion polysilicon layers being inversely doped with the active regions; forming second grooves, the second grooves running through the polysilicon layers and a part of the semiconductor substrate, and reserving parts of the inversion polysilicon layers located on side faces of the second grooves; and, forming buried word line structures in the second grooves.

Abstract: An alignment mark count acquiring method includes: acquiring a first time at which an exposure machine performs exposure of a first wafer, and acquiring a second time at which the exposure machine performs alignment of a second wafer; acquiring a first buffer time between the second time and the first time when the first time is less than the second time; determining a target alignment mark count of the second wafer according to the exposure parameters of the first wafer and the corresponding relationship when the first buffer time is greater than a preset value, wherein the corresponding relationship is the relationship between the exposure parameters and the alignment mark counts, and the corresponding relationship is used to make the first buffer time to be less than or equal to the preset value; and outputting the target alignment mark count.

Abstract: A method for determining the memory power consumption includes: receiving a memory control command and controlling an analog memory to enter different working stages according to the memory control command (S410); acquiring an original current change curve of the analog memory in different working stages (S420); determining a target time period corresponding to a target working stage according to a time sequence of the memory control command (S430); intercepting a stage current change curve corresponding to the target working stage from the original current change curve according to the target time period to obtain a target current change curve (S440); selecting target performance parameters from a memory performance parameter table according to the target working stage (S450); and determining the power consumption of the memory according to the target performance parameters and the target current change curve (S460).

Abstract: A manufacturing method of an integrated circuit memory includes: a substrate is provided; a bit line extending along a first direction is formed on the substrate; a word line extending along a second direction is formed on the bit line; and a vertical storage transistor is formed in an overlapping region where the word line and the bit line are spatially intersected, the vertical storage transistor being located on the bit line, and connected to the bit line.

Abstract: A semiconductor structure includes: a substrate with conductive contact regions; a bit line structure and an isolation wall located on a sidewall of the bit line structure, the isolation wall includes at least one isolation layer including a first isolation part close to the bit line structure and a second isolation part deviating from the same, the second isolation part has doped ions, such that it has a greater hardness than the first isolation part, or has a smaller dielectric constant than the first isolation part; and a capacitor contact hole, which exposes the conductive contact region, and has a top width greater than a bottom width in a direction parallel to an orientation of the bit line structure.

Abstract: A method for testing crosstalk effect includes: obtaining a test signal and an interference input signal; inputting the test signal into a crosstalk effect test circuit obtained by simulation, so as to obtain an interfered signal; and when a rise time of the interfered signal or a fall time of the interfered signal is greater than a preset time threshold, determining that an excessive crosstalk effect exists in an integrated circuit under test. The crosstalk effect test circuit includes a first circuit, N second circuits, and N capacitors. The first circuit is configured to simulate an interfered first signal circuit in the integrated circuit under test; the N second circuits are configured to simulate N second signal circuits that interfere with the first signal circuit in the integrated circuit under test.

Abstract: The present application discloses a diffusion furnace, including: a furnace tube structure including a furnace tube body and a furnace bottom, a bottom of the furnace tube body being connected to the furnace bottom to form a reaction chamber; and a carrying structure including a pedestal and a plurality of cassettes disposed on the pedestal, the pedestal being disposed on the furnace bottom. By disposing the plurality of the cassettes, a height of the furnace tube body can be decreased and a width of the furnace tube body can be increased, thus enlarging a space of equipment repair and maintenance, which is favorable for the repair and maintenance of the equipment.

Abstract: A package structure includes: a substrate, where a plurality of welding pads are disposed on a surface of the substrate, each of the plurality of welding pads includes a bottom layer welding pad and a top layer welding pad which are stacked onto one another, and at least two of peripheral surfaces of the top layer welding pad are protruded relative to peripheral surfaces of the bottom layer welding pad; a chip located on the substrate and spaced apart from the substrate; and a plurality of solder balls, where the plurality of solder balls are welded to the substrate and the chip, and the plurality of solder balls wrap the top layer welding pads.

Abstract: An electrostatic discharge protection structure and a chip are provided. The electrostatic discharge protection structure includes: a semiconductor substrate, an N-type well, a P-type well, a first N-type doped portion, a first P-type doped portion, a second P-type doped portion and a second N-type doped portion. The N-type well and the P-type well are located in the semiconductor substrate. The first N-type doped portion and the second P-type doped portion are located in the P-type well, and the first P-type doped portion and the second N-type doped portion are located in the N-well. The first N-type doped portion has a “T” shape structure, the first P-type doped portion has a “U” shape structure, and a part of the first N-type doped portion is located in a “U” shape opening of the first P-type doped portion.

Abstract: Provided is a semiconductor structure and a method for manufacturing the same, a memory and a method for operating the same. The semiconductor includes a substrate having a plurality of active areas close to a surface of the substrate; a gate structure located in a first structure layer on the substrate, in which the gate structure and the active areas constitute a selective transistor; and an anti-fuse bit structure located in a second structure layer on the first structure layer, and connected with an active area of one selective transistor through a first connecting structure, in which a breakdown state and a non-breakdown state of the anti-fuse bit structure represent different stored data.

Abstract: Provided is an anti-fuse structure, an anti-fuse array and a method for forming the same. The anti-fuse structure includes: a substrate; a switching device including a first gate structure, a second gate structure, a first doped region, a second doped region and a third doped region, the first and the second gate structures being arranged on the substrate, the first and the second doped regions being respectively located in the substrate at two sides of the first gate structure, and the second and the third doped regions being respectively located in the substrate at two sides of the second gate structure; and an anti-fuse device including a third gate structure and the third doped region, the second and the third gate structures being respectively located on the substrate at two sides of the third doped region, and the doped regions being configured to form a source or a drain, respectively.

Abstract: A memory device includes: two calibration resistor interfaces connected to the same ZQ calibration resistor; and a first master chip, first slave chips, a second master chip, and second slave chips, which are commonly connected to the ZQ calibration resistor; in a command mode, a first signal receiver is used to receive a ZQ calibration command, a second signal receiver is used to receive and delay the ZQ calibration command, the first slave chips and the second slave chips start to calibrate based on the ZQ flag signal, and after the calibration is completed, the first slave chips and the second slave chips send a ZQ flag signal through second transmission terminals.

Abstract: An in-memory computing circuit includes an initial computing circuit and a target computing circuit. Herein, the initial computing circuit is configured to perform first operation processing on first data and second data to output a first operation result, and perform second operation processing on the first data and the second data to output a second operation result. The target computing circuit is configured to perform the first operation processing on the second operation result and the first operation result to output a first target result, and perform the second operation processing on the first data and the second operation result to output a second target result.

Abstract: A refresh control circuit includes the following: an address output circuit configured to output a to-be-refreshed address signal including a block address signal and a row address signal; a block decoding circuit configured to: receive the block address signal; decode the block address signal and output a first block selection signal for selecting multiple data blocks from the memory array, in response to that the memory array is subjected to no row hammer attack, or decode the block address signal and output a second block selection signal for selecting one data block from the memory array, in response to that the memory array is subjected to a row hammer attack; and a row decoding circuit, configured to receive the row address signal, decode the row address signal and output a row selection signal.

Abstract: A method for forming a semiconductor structure includes the following operations. A substrate is provided. The substrate includes double heterostructures arrayed along a first direction and a second direction. Each of the double heterostructures includes a first semiconductor layer, a second semiconductor layer and another first semiconductor layer sequentially arranged along the first direction. A forbidden band gap of the first semiconductor layer is different from a forbidden band gap of the second semiconductor layer. The first direction is perpendicular to the second direction, and both the first direction and the second direction are parallel to a direction of a plane where the substrate is located. A double gate structure is formed on sidewalls of each of the double heterostructures along the first direction.

Abstract: A signal masking circuit includes a receiving circuit, a delay control circuit, and a logical operation circuit. The receiving circuit is configured to: receive a signal to be processed and a chip select (CS) signal, and output an initial processing signal and an initial CS signal. The delay control circuit is configured to perform delay and logical control operations on the initial CS signal to obtain a CS masking signal, where a pulse width of the CS masking signal is greater than or equal to two preset clock periods. The logical operation circuit is configured to perform invalid masking on the initial processing signal according to the CS masking signal to obtain a target signal.

Abstract: The data transmission circuit includes: at least two data transmission structures. Each data transmission structure includes a memory transmission terminal, a bus transmission terminal, and an interactive transmission terminal. Data inputted from the memory transmission terminal is outputted through the bus transmission terminal or the interactive transmission terminal. Data inputted from the bus transmission terminal is outputted through the memory transmission terminal or the interactive transmission terminal. Data inputted from the interactive transmission terminal is outputted through the bus transmission terminal or the memory transmission terminal. A control module receives an input control signal and an adjustment control signal that are provided by the memory; the control module is configured to output the input control signal in a delayed manner based on the adjustment control signal, so as to generate an output control signal corresponding to the input control signal.