Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
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Patent number: 11854797Abstract: A method for manufacturing a semiconductor memory includes: providing a portion to be processed, and performing a preset process step on the portion to be processed at least after a minimum waiting time; before performing the preset process step, performing a thermal oxidation process on the portion to be processed; and before performing the preset process step, performing a cleaning process, the cleaning process being used to remove oxides from the surface of the portion to be processed, the oxides being wholly or partly generated by the thermal oxidation process.Type: GrantFiled: February 8, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Haodong Liu
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Patent number: 11854938Abstract: The present disclosure provides an electrostatic protection device and an electrostatic protection circuit. The electrostatic protection device includes: a discharge transistor, located on a substrate for discharging electrostatic charges; and a first pad, located on a first metal layer and electrically connected to a drain region of the discharge transistor; wherein a projection of the first pad on the substrate partially overlaps a projection of the drain region on the substrate.Type: GrantFiled: November 2, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Xin Li, Zhan Ying
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Patent number: 11854642Abstract: A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.Type: GrantFiled: October 15, 2020Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Heng-Chia Chang, Li Ding, Chuanqi Shi
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Patent number: 11853673Abstract: The present disclosure provides a standard cell template and a semiconductor structure. The standard cell template includes a first well region and a second well region, arranged along a first direction; a first gate pattern, located in the first well region and extending along the first direction, for defining a first gate; a second gate pattern, located in the second well region and extending along the first direction, for defining a second gate; and a gate electrical connection pattern, located between the first gate pattern and the second gate pattern, for defining a gate electrical connection structure; where the gate electrical connection structure is arranged on the same layer as the first gate and the second gate to electrically connect the first gate and/or the second gate.Type: GrantFiled: October 20, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Peihuan Wang
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Patent number: 11854605Abstract: A state detection circuit for an anti-fuse memory cell includes: amplifier, having first input terminal connected with first reference voltage, second input terminal connected with first node and output terminal connected with second node; anti-fuse memory cell array, including anti-fuse memory cell sub-arrays, bit lines of sub-arrays are connected with first node, word lines of sub-arrays are connected with controller and each sub-array includes anti-fuse memory cells; first switch element, having first terminal connected with power supply, second terminal connected with first node and control terminal connected with second node; second switch element, having first terminal connected with power supply, second terminal connected with third node and control terminal connected with second node; third switch element, having first terminal connected with third node, grounded second terminal and control terminal connected with controller; and comparator, having first and second input terminals connected with thirdType: GrantFiled: January 7, 2022Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Rumin Ji
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Patent number: 11856748Abstract: The present disclosure discloses a semiconductor memory preparation method and a semiconductor memory, relating to the technical field of semiconductors. The method includes: providing a semiconductor substrate in which transistors are formed and have an array layout; forming a film stack structure on the semiconductor substrate; forming through holes penetrating the film stack structure to expose sources of the transistors; epitaxially growing a storage node contact layer on exposed surfaces of the sources of the transistors; and forming a bottom electrode of a capacitor on a surface of the storage node contact layer.Type: GrantFiled: June 1, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Kui Zhang, Zhan Ying
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Patent number: 11855183Abstract: A method for manufacturing a semiconductor device, including: acquiring a substrate, wherein a gate structure is formed on the substrate; implanting first ions into the substrate to form pre-amorphized regions at two sides of the gate structure respectively; implanting second ions into the pre-amorphized regions to form amorphized regions in the pre-amorphized regions respectively; forming first sidewalls each at a respective one of the two sides of the gate structure; performing a second doping process to form first doped regions in the amorphized regions; forming second sidewalls each at a side of a respective first sidewall; and forming a heavily-doped source region and a heavily-doped drain region in the first doped regions respectively.Type: GrantFiled: August 17, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Wei Huang, Xiaodong Luo
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Patent number: 11854640Abstract: A memory device includes: a plurality of channels, each including a memory cell array, the memory cell array including a normal cell array, the normal cell array including normal memory cells, and each of the normal memory cells being a volatile memory cell; a testing control circuit, configured to control testing of the normal cell array in the plurality of channels in response to a testing instruction, and to determine an access address of a normal memory cell failing the testing in the normal cell array in the plurality of channels to be a failure address; and a non-volatile memory cell array which includes a plurality of non-volatile memory cells and is configured to receive and store the failure address from the testing control circuit.Type: GrantFiled: August 26, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shu-Liang Ning
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Patent number: 11854845Abstract: A system for monitoring an environment can be used for monitoring concentrations of airborne contaminants in a plurality of process areas in a clean room. The system includes: a sampling device, configured to collect environmental samples from process areas and including a system sampling pipeline, the environmental sample including air; an analysis device, connected to an output end of the system sampling pipeline; an air supply device, connected to the system sampling pipeline and configured to provide a purge gas to the system sampling pipeline; and a humidification device, configured to provide water mist and connected between the air supply device and the system sampling pipeline.Type: GrantFiled: September 29, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Xubao Wang, Yunxiao Ding
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Patent number: 11856757Abstract: A semiconductor structure manufacturing method includes that a substrate is provided, in which the substrate includes a substrate layer and a plurality of bit line structures arranged on the substrate layer in a first direction, the substrate layer includes shallow trench isolation structures, active areas, and a plurality of word line structures arranged in a second direction, and two adjacent bit line structures and two adjacent word line structures define a conductive contact region, and the conductive contact region exposing part of a corresponding active area; a conducting layer is formed between the bit line structures, the conducting layer covering the substrate layer, and the conducting layer extending along the first direction; part of the conducting layer is removed with the conducting layer corresponding to the conductive contact region retained to form first capacitor wires; and an isolation layer is formed, which fills gaps between the first capacitor wires.Type: GrantFiled: August 12, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jingwen Lu, Hai-Han Hung
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Patent number: 11854636Abstract: A data sampling circuit includes a frequency dividing circuit, a sampling circuit and a selection circuit. The frequency dividing circuit is configured to receive a first data sampling signal, and perform frequency dividing processing on the first data sampling signal to obtain multiple second data sampling signals associated with respective phases; the sampling circuit is configured to receive the multiple second data sampling signals and a first data signal, and sample the first data signal according to the multiple second data sampling signals to obtain multiple second data signals associated with respective phases; and the selection circuit is configured to receive preamble information and mode register set (MRS) information, and select among the multiple second data sampling signals and the plurality of second data signals according to the preamble information and the MRS information to obtain a target data sampling signal and a target data signal respectively.Type: GrantFiled: April 29, 2022Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zhiqiang Zhang
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Patent number: 11852542Abstract: Methods for measuring a temperature of a wafer chuck and calibrating temperature and a temperature measuring system are provided. The measuring method includes: placing a test wafer on a wafer chuck, where a plurality of semiconductor devices having electrical parameters varying as a function of temperature are formed on the test wafer; making the temperature of the wafer chuck reach set temperatures; measuring the semiconductor devices respectively to obtain electrical parameters corresponding to the semiconductor devices; obtaining actual temperatures of the semiconductor devices according to the electrical parameters and variations, of the electrical parameters, as the function of temperature; and obtaining an actual temperature distribution of the wafer chuck according to the actual temperatures of the semiconductor devices.Type: GrantFiled: July 15, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Shibing Qian, ShihChieh Lin
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Patent number: 11854662Abstract: Memory includes at least one memory chip, a command port and a data port. Each memory chip includes at least one channel. Each channel includes multiple banks that are configured to perform read and write operations alternately. The command port is configured to receive command signals at a preset edge of a command clock, and the command signals are configured to control the read and write operations of the banks. The data port is configured to receive data signals to be written into the banks or transmit data signals at preset edges of a data clock. The command port includes a row address port and a column address port. The row address port is configured to receive a row address signal at a position of a target memory cell, and the column address port is configured to receive a column address signal at a position of the target memory cell.Type: GrantFiled: November 3, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shu-Liang Ning
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Patent number: 11855636Abstract: Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.Type: GrantFiled: July 15, 2022Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yuxia Wang, Kai Tian
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Patent number: 11852976Abstract: An exposure machine and an exposure method are provided in some embodiments of the present disclosure. The exposure machine includes: a detection module, configured to detect whether there are attachments on the surface of a reticle; a cleaning device, configured to clean the attachments on the surface of the reticle; and an exposure module, configured to expose the reticle having no attachments detected.Type: GrantFiled: March 10, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Bin Zou
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Patent number: 11856756Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The method of manufacturing the semiconductor structure includes: providing a substrate; forming, on the substrate, a first initial conductive layer, a sacrificial layer and a first mask layer with a pattern that are stacked sequentially, a thickness of the sacrificial layer being 10 nm-20 nm; and etching, with the first mask layer as a mask, the first initial conductive layer and the substrate to form a bit line (BL) contact region.Type: GrantFiled: April 13, 2022Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Mengdan Zhan
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Patent number: 11854607Abstract: Embodiments of the present application provide a memory structure and a memory layout. The memory structure includes: memory arrays, each including a plurality of memory cells; read-write conversion circuits, each disposed between two adjacent ones of the memory arrays in a first direction, being arranged in a second direction, having a symmetry axis in the second direction, and configured to write external data into the memory cells, or read data from the memory cells, and the first direction being perpendicular to the second direction; sense amplification circuits, symmetrically disposed between two adjacent ones of the memory arrays based on the symmetry axis, coupled to the memory cells in the adjacent ones of the memory arrays; and bias contact point structures, disposed in gaps between the read-write conversion circuits, and configured to set a bias voltage of a well region where the bias contact point structures are located.Type: GrantFiled: April 29, 2022Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yang Zhao, Jaeyong Cha
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Patent number: 11854186Abstract: The present application provides a comparison method and a modeling method for a chip product, a device and a storage medium. According to the method, the chip product is modeled by using a neural network based on a slice sequence of the chip product in advance to obtain a three-dimensional stereoscopic model. When the chip products are compared, a comparison feature is acquired responsive to an operation of a user. For each chip product, a comparison result corresponding to the comparison feature is acquired from the three-dimensional stereoscopic model corresponding to each chip product. Then, the comparison result corresponding to each chip product is displayed.Type: GrantFiled: July 30, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jiemei Zhang, Gehua Shen
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Publication number: 20230410929Abstract: A memory chip test method includes: a mode register write command is sent to a memory chip to control a memory chip to enter a test mode of Write Clock to clock leveling (Wck2ck Leveling); a first preset time is set, and a read and write clock signal is sent to the memory chip after waiting for the first preset time; a predicted value of the Wck2ck Leveling is determined according to the first preset time and a system clock cycle; after sending the read and write clock signal and waiting for a second preset time, a test data output port of the memory chip is detected to obtain a test value; and the test value and the predicted value are compared to determine whether the memory chip is abnormal. A method for testing a Wck2ck Leveling function is provided.Type: ApplicationFiled: January 17, 2023Publication date: December 21, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Beiyou ZHAO, Yu LI, Teng SHI
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Publication number: 20230410876Abstract: A semiconductor device includes: a power down control circuit receiving a power down command signal and a chip selection signal, and generating a power down enable signal and a power down exit signal, here, a logic level of the power down enable signal is converted at a first edge of the power down command signal during a power down stage, and a logic level of the power down exit signal is converted at a second edge of the chip selection signal during a power down exit stage; a power control circuit stopping providing a power voltage according to the power down enable signal during the power down stage, and providing the power voltage according to the power down exit signal during the power down exit stage; and an input buffer circuit transmitting signals during the power down exit stage in response to the power down exit signal.Type: ApplicationFiled: August 12, 2023Publication date: December 21, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yupeng FAN