Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
  • Publication number: 20240008376
    Abstract: A semiconductor structure includes a substrate and a phase-change memory cell located on the substrate. The phase-change memory cell includes a phase-change material layer and a heating layer. The heating layer is located between the phase-change material layer and the substrate, and includes a first portion composed of a first conductive material and a second portion composed of a second conductive material. The first portion surrounds at least a sidewall of the second portion.
    Type: Application
    Filed: January 17, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: YU-CHENG LIAO
  • Publication number: 20240006006
    Abstract: An anti-fuse cell structure includes: a first anti-fuse transistor having a first end and a second end; a first selection transistor having a first end and a second end, the first end of the first selection transistor being electrically connected to the second end of the first anti-fuse transistor; and a Blow Enable (BE) line electrically connected to a first end of the first anti-fuse transistor, and configured to perform programming operation on the first anti-fuse transistor.
    Type: Application
    Filed: April 4, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.,
    Inventor: Chuangming HOU
  • Publication number: 20240005072
    Abstract: A method for checking a data processing circuit includes the following. Performance check files of a plurality of timing sequence logic elements in the data processing circuit are acquired, and the data processing circuit is simulated based on the performance check files of the plurality of timing sequence logic elements, so as to obtain timing sequence information of the respective timing sequence logic elements.
    Type: Application
    Filed: January 31, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zengquan WU
  • Patent number: 11864375
    Abstract: A memory and a method for manufacturing the same are provided. The memory includes: a substrate including an isolation structure and an active area between adjacent isolation structures; a first gate structure, the first gate structure locates in a first groove of the isolation structure, includes a first gate filled in the first groove, and the first gate includes a first conductive layer filled at the bottom of the first groove and a second conductive layer, the second conductive layer locates above the first conductive layer, and the work function of the material of the first conductive layer is greater than that of the material of the second conductive layer; a second gate structure, located in the second groove of the active area, includes a second gate filled in the second groove, and the material of the second gate is the same as that of the second conductive layer.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: ChihCheng Liu
  • Patent number: 11862239
    Abstract: A bit line sense circuit and a memory are disclosed in the present application. The bit line sense circuit includes: L storage unit groups, each storage unit group including H bit lines, both L and H being positive integers greater than or equal to 2; and M sense amplifier groups, configured to write or read storage data to or from the bit lines in the storage unit groups and electrically connected to the L storage unit groups, M being an integer multiple of L or L being an integer multiple of M. Two adjacent bit lines of the H bit lines are connected to the different sense amplifier groups.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Sungsoo Chi, Jia Wang, Ying Wang, Shuyan Jin, Fengqin Zhang
  • Patent number: 11862461
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a base is provided, in which the base includes a first doped area and a second doped area, and an isolation structure is provided between the first doped area and the second doped area; nitridation treatment is performed on the first doped area and the second doped area; and oxidation treatment is performed on the first doped area and the second doped area subjected to the nitridation treatment, to form a first gate oxide layer and a second gate oxide layer respectively.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Tzung-Han Lee
  • Patent number: 11862290
    Abstract: A memory chip stores a characterization parameter for characterizing a process corner of the memory chip, the memory chip further has a reference voltage with an adjustable value, the value of the reference voltage is adjustable based on the characterization parameter, and the memory chip adjusts, based on the reference voltage, a delay from reading out data from a memory cell to outputting the data through a data port.
    Type: Grant
    Filed: April 30, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Patent number: 11860748
    Abstract: A memory test method, a memory test apparatus, a device and a storage medium are provided. The memory test method includes: obtaining a central processing unit (CPU) accessible space of a memory to-be-tested; obtaining a graphics processing unit (GPU) accessible space of the memory to-be-tested; and driving a CPU to run a test program based on the accessible space of the CPU, to access the memory to-be-tested through a bus of memory to-be-tested, when the CPU runs the test program, the CPU controls a GPU to access the memory to-be-tested based on the accessible space of the GPU through the bus of memory to-be-tested.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiaofeng Xu
  • Patent number: 11862233
    Abstract: The present application relates to the field of semiconductors, in particular, to the field of Dynamic Random Access Memories (DRAMs), and provides a method and system for detecting a mismatch of a sense amplifier. The method creates a sense amplifier by delaying switch-on of a positive channel-metal-oxide-semiconductor (PMOS) transistor or a negative channel-metal-oxide-semiconductor (NMOS) transistor in the sense amplifier and shortening a row precharge command period (tRP).
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Dong Liu, Tianhao Diwu, Xikun Chu
  • Patent number: 11860226
    Abstract: Embodiments of the present application provide a time offset method and device for a test signal. When a signal source sends a test signal to a DUT on a test platform, the offset device can determine a time delay caused by impedance matching of the test signal to the DUT at the upper side of each test location, and conduct time offset for TCK signals sent by the signal source to different DUTs according to the time delay.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Liang Chen, Xuemeng Lan
  • Patent number: 11862516
    Abstract: A semiconductor structure manufacturing method according to the embodiments of the present application includes the following steps of: providing a semiconductor substrate; forming a first reaction layer on the semiconductor substrate; forming a second reaction layer on the first reaction layer; and thermally reacting at least a portion of the first reaction layer with at least a portion of the second reaction layer, to form an amorphous diffusion barrier layer. This amorphous diffusion barrier layer is an amorphous body with no grain boundary therein. As a result, the diffusion path for metal atoms is cut off, thereby improving the barrier effect of the barrier layer efficiently and solving the circuit performance issue caused by metal atom diffusion.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Huiwen Tang
  • Patent number: 11862285
    Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module configured to read data in a storage unit on a first or second bit line; a control module electrically connected to the amplification module. When data in the storage unit on the first bit line is read, in a first amplification phase of the sense amplifier, the control module configures the amplification module to include a first current mirror structure and connects a mirror terminal of the first current mirror structure to the second bit line; when data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module configures the amplification module to include a second current mirror structure and connects a mirror terminal of the second current mirror structure to the first bit line.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: January 2, 2024
    Assignees: ANHUI UNIVERSITY, CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Zhiting Lin, Jianqing Li, Jun He, Zhan Ying, Xin Li, Kanyu Cao, Wenjuan Lu, Chunyu Peng, Xiulong Wu, Junning Chen
  • Patent number: 11862266
    Abstract: The present disclosure provides a chip detection method and a chip detection apparatus. The chip detection method includes: providing a chip to be tested, the chip including a power pump region, and the power pump region including a plurality of power pump structures; detecting a dim light signal emitted from the power pump region when the chip is in a preset working mode; and determining whether the dim light signal matches a corresponding power pump working mode in the preset working mode, and if not, confirming that the power pump region has a defect, the power pump working mode including a working state of the power pump structures in the power pump region.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jianbo Zhou
  • Patent number: 11862232
    Abstract: A circuit and method for data transmission, and a storage apparatus are provided. A mode register decoding module is configured to generate a mode register unselected enable signal, a mode register read enable signal, or a mode register write enable signal according to received mode register address information, a mode register read control signal, or a mode register write control signal. A mode register read-write module is configured to: cache data on data line according to mode register write enable signal in write state, and output selected data and unselected data after setting the unselected data to zero according to the mode register read enable signal and the mode register unselected enable signal in a read state. The logic gate module is configured to calculate an OR value of the data outputted by each mode register read-write module in the read state and output a calculation result.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zhiqiang Zhang
  • Patent number: 11862279
    Abstract: A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Bo Yang, Xiaodong Luo
  • Patent number: 11862494
    Abstract: A crane monitoring system includes a first detection apparatus, a processing apparatus and a second detection apparatus. The first detection apparatus is configured to detect a position of a crane, to send a first detection signal when the crane is located above a Front Opening Unified Pod (FOUP) load port of a semiconductor processing device, and to send a second detection signal when the crane leaves a space above the FOUP load port. The processing apparatus is configured to generate a start control signal responsive to receiving the first detection signal, and to generate a stop control signal responsive to receiving the second detection signal. The second detection apparatus is configured to start a detection of whether there is a foreign matter between the crane and the FOUP load port after receiving the start control signal, and to stop the detection after receiving the stop control signal.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Wei Feng
  • Patent number: 11861232
    Abstract: Embodiments of the present disclosure relate to the technical field of semiconductors and provide a storage system and a data writing method thereof. The storage system is configured to: enter a write data copy mode in response to a write-copy enable signal; if at least two groups of data in multiple groups of data exported from multiple data ports are a same in the write data copy mode, define the at least two groups of data as a category; generate an identification signal that is used to indicate a data copy; transmit one group of data in the category to an interface of a memory array; and disconnect a transmission path between a data port corresponding to another group of data in the category and another interface of the memory array, wherein the memory array, in response to the write-copy enable signal and the identification signal.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kangling Ji
  • Patent number: 11859153
    Abstract: A method for cleaning a substrate includes the following: exposing the substrate to a cleaning agent to remove impurities on a surface of the substrate; exposing the substrate to a dewetting chemical agent in a liquid phase to remove the cleaning agent on the surface of the substrate; solidifying the dewetting chemical agent in the liquid phase remaining on the surface of the substrate to obtain the dewetting chemical agent in a solid phase; and sublimating and removing the dewetting chemical agent in the solid phase.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shih-Hung Lee
  • Patent number: 11861451
    Abstract: A method for chip collection and a method for chip positioning are provided. The method for chip collection includes that: an image to be detected is obtained; chip position information of a comparison image with a highest matching degree with the image to be detected is obtained from a database; a position of each of detection regions in the image to be detected is obtained based on the chip position information; an image of the detection region is obtained based on the position of each detection region; it is determined whether the image of the detection region includes the chip code image; and when the image of the detection region includes the chip code image, a chip code corresponding to the chip code image identified and the chip code is stored in the database.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yui-Lang Chen
  • Patent number: 11862222
    Abstract: A refresh circuit includes: a refresh control module configured to receive a refresh command to output a row address refresh signal, the row address refresh signal being outputted a number of times of a preset value each time the refresh command is received; and further configured to receive a temperature signal to adjust the preset value, the higher a temperature represented by the temperature signal, the greater the adjusted preset value; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh.
    Type: Grant
    Filed: November 27, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yinchuan Gu, Geyan Liu