Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
  • Publication number: 20240021265
    Abstract: A memory test method includes: obtaining a preset memory and a memory to be tested; setting the memory to be tested as a reserved memory; starting an operating system, wherein the operating system runs in the preset memory; and executing a memory test program to test the memory to be tested, wherein the memory test program runs in the preset memory.
    Type: Application
    Filed: June 7, 2021
    Publication date: January 18, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiaolei LI
  • Publication number: 20240021460
    Abstract: A semiconductor etching apparatus includes: a backing ring, a supporting mechanism, an edge ring and a temperature control mechanism. The edge ring is arranged between the backing ring and the supporting mechanism. The temperature control mechanism includes a heating unit arranged below the edge ring. The temperature control mechanism further includes a temperature controller electrically connected with the heating unit.
    Type: Application
    Filed: June 17, 2021
    Publication date: January 18, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Faming ZHANG
  • Publication number: 20240023304
    Abstract: A method for manufacturing a memory includes: providing a substrate, capacitor contact pads being formed in the substrate; forming a laminated structure on the substrate, the laminated structure including a first laminated structure formed on the substrate and a second laminated structure formed on the first laminated structure; forming first through holes in the second laminated structure; forming a protective layer on side walls of the first through holes, the protective layer in the first through holes enclosing second through holes; and etching the first laminated structure along the second through holes to form third through holes, the third through holes exposing the capacitor contact pads.
    Type: Application
    Filed: July 5, 2021
    Publication date: January 18, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tao LIU, JUN XIA, Kangshu ZHAN, Sen LI, Qiang WAN, Penghui XU
  • Patent number: 11875835
    Abstract: A memory and a read and write method of memory can prevent the magnetic random-access memory (MRAM) from being easily damaged or degraded by excessive write current during use, and increase memory integration density. The memory includes: a storage unit, comprising a storage element; a source line, electrically connected to a first end of the storage element; the memory is configured to change a storage state of the storage element by a first current and a second current, the first current flowing through the storage element and the second current flowing through the source line without flowing through the storage element.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Baolei Wu, Yulei Wu, Xiaoguang Wang, Erxuan Ping
  • Patent number: 11875045
    Abstract: A semiconductor memory and a method for density configuration of a bank of the semiconductor memory are provided. The method includes: determining a target bank to be configured of the semiconductor memory; determining a density configuration parameter of the target bank, the density configuration parameter being configured to represent a density to be configured for the target bank; determining a target code from a set of codes of the target bank based on the density configuration parameter of the target bank, the target code corresponding to a storage region to be trimmed in the target bank; generating, based on the target code, a region selection signal configured to select the storage region to be trimmed in the target bank; and trimming the storage region to be trimmed based on the region selection signal to configure the density of the target bank.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jixing Chen, Weibing Shang
  • Patent number: 11877440
    Abstract: The disclosure relates to a buried bit line and a forming method thereof, the buried bit line is formed in a bit line slot of a substrate, the buried bit line includes a first bit line layer formed in the bit line slot, a first blocking layer and a second bit line layer. A top of the first bit line layer is lower than a surface of the substrate. The first blocking layer is at least partially formed between the first bit line layer and an inner wall of the bit line slot. The second bit line layer is formed in the bit line slot and configured to communicate the first bit line layer with a drain region in the substrate.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Gongyi Wu, Yong Lu, Penghui Xu
  • Patent number: 11875053
    Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and a precharge module configured to set an initial state of the global bus to Low.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Liang Zhang
  • Patent number: 11874324
    Abstract: The present disclosure relates to a device for carrying a chip, and a device and a method for testing a chip. The device for carrying a chip is configured to fasten chips of different sizes, and includes a support box and a plurality of first elastic snap rings. The support box is configured to carry a chip. A first connection terminal of the first elastic snap ring is provided on a first inner side wall of the support box, a second connection terminal of the first elastic snap ring is suspended, and is configured to be in contact with the chip and provide a pressure in a first direction for the chip because an elastic body of the first elastic snap ring is in an elastically compressed state.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jinrong Huang
  • Patent number: 11876651
    Abstract: A driving adjustment circuit and an electronic device are provided. The driving adjustment circuit includes a first NOT gate module, second NOT gate module and third NOT gate module sequentially connected. An input terminal of the first NOT gate module and an output terminal of the third NOT gate module are connected to a signal terminal. The first NOT gate module acquires a to-be-driven signal from the signal terminal and perform a NOT operation on the to-be-driven signal to obtain a first adjustment signal. The second NOT gate module receives the first adjustment signal and performing the NOT operation on the first adjustment signal to obtain a second adjustment signal, when the driving adjustment circuit is in an ON state. The third NOT gate module receives the second adjustment signal and perform voltage adjustment processing on the to-be-driven signal at the signal terminal according to the second adjustment signal.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yinchuan Gu
  • Patent number: 11876064
    Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a metal barrier layer, and a solder layer. The metal pad is arranged on the semiconductor substrate; the bump is arranged on the metal pad; the metal barrier layer is arranged on the side of the bump away from the metal pad; the metal barrier layer contains a storage cavity; the sidewall of the metal barrier layer is configured with an opening connecting to the storage cavity; the solder layer is arranged inside the storage cavity, and the top side of the solder layer protrudes from the upper side of storage cavity. During the flip-chip soldering process, solder is heated to overflow, the opening allows the solder flow out through the opening. The openings achieve good solder diversion in overflow, thus mitigating the problem of solder bridging between bumps.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Ling-Yi Chuang
  • Patent number: 11874609
    Abstract: A temperature control device and a temperature control method are provided. The temperature control device is located at an interface between a photoresist coating and developing machine and a lithography machine and includes: a temperature detection device, a gas flow generator and a controller. The temperature detection device and the gas flow generator are respectively connected to the controller. The temperature detection device is configured to detect an actual temperature at the interface in real time. The gas flow generator is at least configured to generate a gas flow sealing knife around the interface. The controller is configured to control the gas flow generator to generate the gas flow sealing knife responsive to that the actual temperature detected by the temperature detection device is not equal to the target temperature, to control the actual temperature at the interface to reach the target temperature through the gas flow sealing knife.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Enhao Chen, Zhiyong Hu, Jinping Sun
  • Patent number: 11877432
    Abstract: A capacitor structure and a method of preparing the same are provided. The method includes the followings. A substrate is provided. A stacked layer is formed on the substrate. A plurality of first via holes penetrating through the stacked layer are formed. The first via hole is filled with a conductive material to form a conductive pillar. A plurality of second via holes penetrating through the stacked layer are formed at a preset radius with the conductive pillar as an axis. The second via hole surrounds the conductive pillar circumferentially. The second via hole is filled with the conductive material to form an annular top electrode with a second gear.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jun Xia
  • Patent number: 11877441
    Abstract: The present application provides a memory and a memory fabricating method. The memory includes a substrate, on which is disposed a separation layer, in which are arranged plural bitlines spaced apart from one another, the plural bitlines are arranged along a first direction, and each bitline is S-shaped. The method of fabricating the memory comprises the following steps: providing a substrate; forming on the substrate plural bitline grooves; forming in each bitline groove a first separation layer; forming bitlines on the first separation layer; forming a second separation layer on the bitlines; removing the substrate between adjacent separation walls, the separation wall including the first separation layer, the bitlines, and the second separation layer; and forming a third separation layer in a space between the adjacent separation walls, the third separation layer, the second separation layer, and the first separation layer together forming a separation layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengzhu Qiao, Tao Chen
  • Publication number: 20240014188
    Abstract: A semiconductor package assembly and manufacturing method are provided. The assembly includes: a base plate having a first surface; a chip stacking structure located on the base plate, the chip stacking structure including multiple chips sequently stacked in a direction perpendicular to the base plate and being electrically connected to the first surface; an interposer located on the chip stacking structure and having a first interconnection surface, the first interconnection surface having first and second interconnection regions, and the first interconnection region being electrically connected to the base plate; and a molding compound sealing the chip stacking structure, interposer and first surface. The first interconnection region is not sealed by the molding compound and the second interconnection region is sealed by the compound. There is a preset height between a top surface of the molding compound on the second interconnection region and the first interconnection region.
    Type: Application
    Filed: September 23, 2022
    Publication date: January 11, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xiaofei SUN, Changhao QUAN
  • Publication number: 20240013825
    Abstract: A control apparatus includes: a receiving circuit, configured to receive a read clock signal from the memory, and output the read clock signal; a clock circuit, configured to generate a first internal clock signal; a selection circuit, configured to receive the read clock signal and the first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal; and a latch circuit, configured to receive the target read clock signal and a read data signal sent by the memory, and perform latch processing on the read data signal by using the target read clock signal.
    Type: Application
    Filed: January 14, 2023
    Publication date: January 11, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jingwei CHENG
  • Publication number: 20240014189
    Abstract: A semiconductor package structure includes: a first base plate provided with a first surface; a first chip stack body located on the first base plate, where the first chip stack body includes a plurality of first semiconductor chips successively stacked onto one another in a direction perpendicular to the first base plate, and is electrically connected to the first surface of the first base plate; an interposer layer located on the chip stack body and provided with a first interconnection surface, where the first interconnection surface is provided with a first interconnection region electrically connected to the first base plate and a second interconnection region; and a molding layer configured to seal the first chip stack body, the interposer layer and the first surface of the first base plate. The first interconnection region is unsealed by the molding layer, and the second interconnection region is sealed by the molding layer.
    Type: Application
    Filed: January 13, 2023
    Publication date: January 11, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xiaofei SUN, Changhao QUAN
  • Publication number: 20240014190
    Abstract: A semiconductor package structure includes a first package structure and a second package structure. The first package structure includes a chip stacking structure and a molding compound. A first conductive block is disposed on the chip stacking structure. The molding compound wraps the chip stacking structure and exposes the first conductive block. The second package structure is disposed on the chip stacking structure and electrically connected to the first conductive block. A gap is formed between the first package structure and the second package structure.
    Type: Application
    Filed: February 8, 2023
    Publication date: January 11, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Mingxing ZUO
  • Publication number: 20240015954
    Abstract: A memory includes a substrate; a plurality of bit lines on the substrate, which are parallel to each other and extend in a first direction; a plurality of active pillars on the bit lines, bottom ends of which are connected to the bit lines; a plurality of word lines parallel to each other and extending in a second direction, which surround outer sidewalls of the active pillars, and expose top ends of the active pillars, the active pillars and the word lines jointly constitute vertical memory transistors of the memory; and a plurality of capacitors and a plurality of connecting pads, each of the capacitors is located on each of the active pillars, each of the connecting pads is located between the active pillar and the capacitor.
    Type: Application
    Filed: August 13, 2023
    Publication date: January 11, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: CHIH-CHENG LIU
  • Patent number: 11869952
    Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: forming an active region on a substrate; forming at least one trench in the active region, the trench at least dividing the active region into a source region on one side of the trench and a drain region on the other side of the trench; and forming an elevated source region and an elevated drain region on the source region and the drain region respectively.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kang You, Jie Bai
  • Patent number: 11868783
    Abstract: Disclosed are a method of underlying drive forwarding and a multi-core system implemented based on a UEFI, which can increase a running speed of the multi-core system implemented based on a UEFI. The underlying drive forwarding method is configured for underlying drive forwarding of a multi-core system. The multi-core system is implemented based on a UEFI and includes an application processor and a bootstrap processor. The bootstrap processor is provided with an execution interface configured to call underlying hardware. The application processor is configured with an instruction interface corresponding to the execution interface.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yang Wang, Dan Lu, Hao He