Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
  • Patent number: 11871564
    Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming an initial trench in the substrate; forming a sacrificial layer, the sacrificial layer including a first portion and a second portion, the first portion filling the initial trench and the second portion covering an upper surface of the substrate and an upper surface of the first portion; forming a division groove in the second portion, to pattern the second portion into a sacrificial pattern, the sacrificial pattern being arranged corresponding to the first portion; forming a filling layer in the division groove, the filling layer filling the division groove; removing the sacrificial pattern and the first portion, to form a word line trench; and forming a buried gate word line in the word line trench.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yexiao Yu
  • Patent number: 11869610
    Abstract: A storage device includes a storage circuit, a reading circuit, a first check circuit, and a second check circuit. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays which are arranged alternately. A first data wire is electrically connected to each of the sense amplifier arrays. The reading circuit is configured to read data on the first data wire. Both the first check circuit and the second check circuit are electrically connected to the reading circuit. The reading circuit is configured to transmit a part of the read data to the first check circuit for error checking and/or correcting, and transmit another part of the read data to the second check circuit for error checking and/or correcting. The data transmitted to the first check circuit and the data transmitted to the second check circuit are respectively from adjacent sense amplifier arrays.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jia Wang
  • Patent number: 11867497
    Abstract: The present disclosure discloses a method for measuring the film thickness of a semiconductor device. The measuring method includes: providing a reference spectrogram of a main storage region of a reference semiconductor device; obtaining a first measured spectrogram of a main storage region of a semiconductor device to be measured; adjusting a thickness parameter of a target film in the main storage region of the reference semiconductor device within a preset range based on the reference spectrogram, obtaining an adjusted reference spectrogram, and comparing the first measured spectrogram with the adjusted reference spectrogram; if the similarity between the first measured spectrogram and the adjusted reference spectrogram is greater than a first preset value, using the thickness parameter corresponding to the adjusted reference spectrogram as the thickness of the target film in the main storage region of the semiconductor device to be measured.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yongshang Sheng
  • Patent number: 11867758
    Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chuanqi Shi, Heng-Chia Chang, Li Ding, Jie Liu, Jun He, Zhan Ying
  • Patent number: 11871562
    Abstract: A method for forming a storage node contact structure and semiconductor structure are provided. The method includes providing a substrate having a surface on which bit line structures are formed; forming a groove at a part, corresponding to an active region, of bottom of the contact hole; and growing a silicon crystal from the groove in the contact hole by using an epitaxial growth process, and controlling growth rates of the silicon crystal in a first and second directions in a growth process to enable the growth rate of the silicon crystal in the first direction to be greater than the growth rate of the silicon crystal in the second direction at beginning of growth and enable the growth rate of the silicon crystal in the first direction to be equal to the growth rate of the silicon crystal in the second direction at end of the growth.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Erxuan Ping, Zhen Zhou, Lingguo Zhang, Weiping Bai
  • Patent number: 11867755
    Abstract: The present disclosure provides a memory device test method, apparatus, and system, a medium, and an electronic device. The memory device test method includes: determining an operation path according to position coordinates of a target test platform and current position coordinates of a memory device; setting a movable apparatus according to the operation path, such that the movable apparatus moves the memory device into the target test platform according to the operation path; controlling the target test platform to test the memory device according to a target test program; and monitoring a test result of the memory device in real time, and storing the test result of the memory device into a database.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yu Yu
  • Patent number: 11871560
    Abstract: The application provides a method for manufacturing a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors. The method for manufacturing the semiconductor structure includes: providing a base; sequentially stacking an initial conductive layer, an initial first dielectric layer, an initial first mask layer, an initial second dielectric layer, an initial second mask layer and a photoresist layer with a pattern on the base; and etching part of the initial second mask layer, part of the initial second dielectric layer and part of the initial first mask layer by taking the photoresist layer as a mask, so as to form a second dielectric layer with a trapezoidal structure which is of a structure with small top and large bottom.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mingxia Cheng, Yang Chen
  • Patent number: 11869930
    Abstract: A method for forming a semiconductor structure and a semiconductor structure are provided. The method includes: a stacked structure is formed on a surface of a substrate, the stacked structure including supporting layers and sacrificial layers which are alternately stacked; a buffer layer is formed on a surface of the stacked structure facing away from the substrate; capacitor holes penetrating through the stacked structure and the buffer layer and exposing capacitor contacts are formed; a first electrode layer covering inner walls of the capacitor holes is formed; an etching window penetrating through the buffer layer is formed; part of the supporting layers and all of the sacrificial layers in the stacked structure are removed along the etching window; the buffer layer is removed; and a dielectric layer and a second electrode layer are formed to form a capacitor.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yong Lu
  • Patent number: 11869570
    Abstract: A refresh counter circuit, a refresh counting method and a semiconductor memory are provided. The refresh counter circuit includes: a first signal generator that is configured to generate a first carry signal according to each of refresh pulse signals generated by a received refresh command; a second signal generator that is configured to generate a second carry signal according to a last refresh pulse signal generated by the received refresh command; a first counter that is configured to perform signal inversion according to the first carry signal and generate a first output signal; and a second counter that is configured to count the refresh command according to the second carry signal and generate a second output signal; where the refresh command generates at least two refresh pulse signals.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jixing Chen
  • Patent number: 11869774
    Abstract: A method for improving an etching rate of wet etching involves an etching reaction chamber used for etching work. The etching reaction chamber is connected with an etchant supply mechanism. The etchant supply mechanism is connected with a purified water supply mechanism. The purified water supply mechanism injects purified water into the etchant supply mechanism according to a change range of pH of the etchant in the etchant supply mechanism to ensure that a hydrogen ion concentration and a fluoride ion concentration of the etchant in the etchant supply mechanism are stable.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Nannan Zhang, Yen-Teng Huang
  • Patent number: 11867745
    Abstract: Provided are a parasitic capacitance detection method, a memory, and a readable storage medium, relating to the field of semiconductor technologies. The detection method comprises: providing a plurality of semiconductor devices for testing, all the semiconductor devices being the same in a number of sources, a number of drains, a number of active layers, a number of gates, a number of wires and a cross-sectional area of the wire, all the semiconductor devices being different in a length of the wire therein; determining a capacitance between the wire per unit length and the gate in the semiconductor device, the capacitance between the wire per unit length and the gate being considered as a parasitic capacitance per unit length; determining a corresponding wire length of a to-be-detected semiconductor device; and determining a parasitic capacitance of the to-be-detected semiconductor device.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shibing Qian
  • Patent number: 11869929
    Abstract: A laminated capacitor and a method for manufacturing the same are provided. The method includes operations of providing a substrate; forming a first isolation insulation spacer and a plurality of discrete bottom bonding pads on the substrate; forming a sub-capacitor structure on the bottom bonding pads, which comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium located between the bottom electrodes and the top electrodes, wherein the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes in one-to-one correspondence; and repeatedly performing an operation of forming a connection structure and the sub-capacitor structure for N times on the sub-capacitor structure, such that N connection structures and N+1 sub-capacitor structures are alternately arranged along a direction perpendicular to the substrate, wherein N is an integer greater than or equal to 1.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jun Xia, Shijie Bai
  • Patent number: 11867760
    Abstract: The present application provides a parameter setting method and apparatus, a system, and a storage medium. The parameter setting method includes: obtaining first setting values of multiple memory parameters and storage locations of the multiple memory parameters in a non-volatile memory; generating a first parameter setting instruction according to the first setting value and the storage location of each memory parameter; and sending the first parameter setting instruction to a test device, so that the test device sets the memory parameter stored at the storage location in the non-volatile memory as the first setting value.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Hao He
  • Patent number: 11869576
    Abstract: A word line driving circuit includes a driving circuit and a control circuit. The control circuit includes a control sub-circuit, a first switching sub-circuit and a second switching sub-circuit. The first switching sub-circuit is provided with: a control terminal electrically connected with the control sub-circuit, a first terminal electrically connected with a first power supply voltage, and a second terminal electrically connected with a third input terminal of the driving circuit. The second switching sub-circuit is provided with: a control terminal electrically connected with the control sub-circuit, a first terminal electrically connected with a second power supply voltage, and a second terminal electrically connected with the third input terminal of the driving circuit. The second power supply voltage is greater than a ground voltage.
    Type: Grant
    Filed: February 19, 2022
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Cheng-Jer Yang
  • Patent number: 11869578
    Abstract: A memory bank includes at least one storage module, each storage module including a read-write control circuit, a column decoding circuit and a plurality of storage arrays, the plurality of storage arrays being divided into a first unit and a second unit; a first decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the first unit; a second decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the second unit; a first data signal line; and a second data signal line.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weibing Shang, Hongwen Li
  • Publication number: 20240008268
    Abstract: A semiconductor device includes a substrate including a memory region and a peripheral region located at an outer side of the memory region; a memory structure located above the memory region and including a memory array and signal lines, the memory array at least including memory cells spaced apart from each other along a first direction, and the signal lines being electrically connected with the memory cells, the first direction is perpendicular to the top surface of the substrate; a peripheral structure located above the peripheral region and including peripheral stacked layers, peripheral circuits located above the peripheral stacked layer, and peripheral leads located above the peripheral circuits, one end of each peripheral lead being electrically connected with at least one of peripheral circuits, and the other end being electrically connected with at least one of signal lines.
    Type: Application
    Filed: January 14, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tao DOU, JIE BAI
  • Publication number: 20240008248
    Abstract: A method for manufacturing a semiconductor structure includes the following operations. A structure to be etched is provided. An etched hole is formed in the structure to be etched. Multiple conducting material layer deposition processes are performed until the conducting material layer fills up the etched hole without a void. The method further includes annealing the deposited conducting material layer after at least some of the conducting material layer deposition processes.
    Type: Application
    Filed: January 13, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: YOUMING LIU
  • Publication number: 20240006175
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes: a substrate is provided, the substrate being provided with a first device area and a second device area with different doping types; a gate oxide layer which covers the first device area and the second device area is formed; a gate conductive layer which covers the gate oxide layer is formed; a first gate structure is formed on the first device area, the first gate structure including the gate conductive layer and the gate oxide layer; a second gate structure is formed on the second device area, the second gate structure including the gate conductive layer and the gate oxide layer. In the first device area and the second device area, the gate conductive layer always covers the gate oxide layer.
    Type: Application
    Filed: January 17, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kang You, Jie Bai
  • Publication number: 20240006281
    Abstract: A semiconductor structure includes: a substrate including a first surface; a first solder pad located on the first surface; a transferring part located on the first solder pad, in which the transferring part includes a first subpart covering the first solder pad and a second subpart covering the first subpart, and orthographic projections of the first subpart and the first solder pad on the first surface fall within an orthographic projection of the second subpart on the first surface; and a solder ball located on the second subpart.
    Type: Application
    Filed: January 20, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zongzheng LU
  • Publication number: 20240006319
    Abstract: A semiconductor structure includes a base provided with a conductive contact hole, a metal sulfide layer formed in the conductive contact hole and covering a bottom wall of the conductive contact hole, a semi-metal layer formed on a surface of the metal sulfide layer, a barrier layer covering a surface of the semi-metal layer and a sidewall of the conductive contact hole and a conductive contact structure disposed in an accommodation hole delimited by the barrier layer.
    Type: Application
    Filed: August 11, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shuai GUO