Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
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Publication number: 20230397388Abstract: A semiconductor structure includes a substrate, first transistor columns and second transistor columns on the substrate. The first transistor columns and the second transistor columns are alternately arranged. A first transistor column includes a plurality of first transistors arranged in a first direction. A second transistor column includes a plurality of second transistors arranged in the first directions. The plurality of first transistors in the first transistor column are electrically connected to the plurality of second transistors in the second transistor column in one-to-one correspondence. A length direction of the first transistor is the same as a length direction of the second transistor. A center of the first transistor is offset from a center of the second transistor in the first direction.Type: ApplicationFiled: February 4, 2023Publication date: December 7, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Runping WU, DAEJOONG WON
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Publication number: 20230395543Abstract: A package structure includes an isolation layer with multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer. Each via exposes a respective part of an interconnection layer arranged on a surface of a semiconductor functional structure. Each first pad is formed by a respective part of the interconnection layer exposed by the corresponding via, N is a positive integer greater than 1. Each RDL covers the isolation layer and is electrically connected to a corresponding one of the N first pads. The first insulating layer is formed on the RDLs and exposes a part area of each RDL. The exposed part areas of at least some of the RDLs includes second pads and third pads. The center point of each second pad has the same offset direction and the same offset distance with respect to the center point of the corresponding first pad.Type: ApplicationFiled: January 10, 2023Publication date: December 7, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Kai TIAN, Hongwen LI, Liang CHEN, Wei JIANG
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Patent number: 11835492Abstract: Embodiments of the present application provide a method for preparing a sample for wafer level failure analysis. The method includes that: a plurality of splitting points are formed on a surface of a selected region of a to-be-analyzed sample along a preset direction, the plurality of splitting points being arranged in a straight line; and the to-be-analyzed sample is split by taking the straight line where the plurality of splitting points are located as a splitting line, to expose a cross section of a side surface of the to-be-analyzed sample and form the sample for the wafer level failure analysis.Type: GrantFiled: August 20, 2021Date of Patent: December 5, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Wen-Lon Gu
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Patent number: 11837508Abstract: The present application relates to a semiconductor device and a manufacturing method thereof. The method includes: obtaining a substrate, a first device region, a second device region and a high-k gate dielectric layer film being formed on the substrate; forming, on the substrate, a barrier layer structure covering the high-k gate dielectric layer film at the second device region; forming a covering layer film including a first metal element on the substrate; and diffusing the first metal element in the covering layer film towards the high-k gate dielectric layer film at the first device region using an annealing process, the barrier layer structure preventing the first metal element from being diffused towards the high-k gate dielectric layer film at the second device region; wherein the first device region and the second device region have opposite conduction types.Type: GrantFiled: May 25, 2021Date of Patent: December 5, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jie Bai, Kang You
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Patent number: 11837309Abstract: A processing method of chip probing data includes: determining a new fail bit generated in an already completed chip probing process; acquiring repair record of the new fail bit, and repair records of bits adjacent to the new fail bit; analyzing the repair records to determine attribute information of the new fail bit and the adjacent bits, the attribute information including at least one of address information, redundant circuit information, element pattern of the new fail bit and chip probing flow; performing classification learning according to the attribute information to acquire a fail bit prediction model; and predicting fail bits to be chip-probed through the fail bit prediction model.Type: GrantFiled: November 20, 2021Date of Patent: December 5, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Lei Yang, Yui-Lang Chen
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Patent number: 11837322Abstract: A memory is provided. The memory includes a control chip (114) and a plurality of memory chips (100). The plurality of memory chips are electrically connected to the control chip (114) by sharing a channel (01). The plurality of memory chips (100) are configured to adopt the same clock signal, and each of the plurality of memory chips (100) is configured to perform information interaction with the control chip (114) in a different clock state of the clock signal.Type: GrantFiled: August 24, 2021Date of Patent: December 5, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shu-Liang Nin
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Patent number: 11837304Abstract: The present disclosure provides a detection circuit, including: a generation unit provided with a plurality of output terminals and configured to generate random detection data and output one bit of the random detection data through each output terminal; a first drive unit provided with a plurality of first input terminals connected to the plurality of output terminals of the generation unit in one-to-one correspondence and a plurality of output terminals connected to a memory array, and configured to transmit the random detection data to the memory array, wherein the memory array is configured to store the random detection data; and a comparison unit provided with a plurality of first input terminals connected to the plurality of output terminals of the generation unit in one-to-one correspondence and a plurality of second input terminals connected to the memory array.Type: GrantFiled: June 8, 2022Date of Patent: December 5, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Enpeng Gao
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Publication number: 20230389339Abstract: A semiconductor structure includes a first semiconductor layer and a second semiconductor layer bonded to each other. The first semiconductor layer includes a first redistribution line, and the first redistribution line has a first projection length on a bonding surface of the first semiconductor layer and the second semiconductor layer. The second semiconductor layer includes a second redistribution line, and the second redistribution line has a second projection length on the bonding surface. The first projection length is different from the second projection length. The first redistribution line is electrically connected to the second redistribution line. A method for forming the same is also provided.Type: ApplicationFiled: February 15, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Chao LIN
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Publication number: 20230384347Abstract: A package substrate, an apparatus for testing power supply noise, and a method for testing power supply noise are provided. The package substrate includes multiple pad arrays, and each of the multiple pad arrays at least includes power supply pads. Power supply pads belonging to a same power supply type in the multiple pad arrays are divided into a test pad and a power supply pad set. The power supply pad set includes power supply pads, other than the test pad, among the power supply pads belonging to the same power supply type, all the power supply pads in the power supply pad set are electrically connected together, and the test pad is configured to perform noise testing of at least one internal power supply corresponding to the same power supply type in a chip to be tested.Type: ApplicationFiled: September 23, 2022Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Honglong SHI, Maosong MA, Jianbin LIU
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Publication number: 20230384818Abstract: A data processing circuitry includes: a preprocessing circuit, configured to receive an initial data signal and generate a data signal to be processed and an auxiliary data signal according to the initial data signal; and a drive circuit, connected with the preprocessing circuit and configured to: adjust an initial calibration code according to a preset scenario, to obtain a target calibration code; adjust a value of a drive resistance of the drive circuit according to the target calibration code; and adjust a drive capability of the data signal to be processed according to the auxiliary data signal and the adjusted drive resistance, to generate a target data signal.Type: ApplicationFiled: August 11, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yinchuan GU
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Publication number: 20230389286Abstract: The disclosure relates to the technical field of semiconductors, and to a memory, a semiconductor structure and a method for same. The method includes: providing a substrate, the substrate including a plurality of conductive contact plugs in array distribution and insulation layers separating the conductive contact plugs; and forming a plurality of capacitive layers stacked and distributed in a direction perpendicular to the substrate on a surface of the substrate, each of the capacitive layers including a plurality of capacitances distributed at intervals, and the capacitances being respectively connected to different conductive contact plugs. According to the method, the storage capacity of capacitances can be increased, and product yield can be enhanced.Type: ApplicationFiled: August 11, 2022Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jingwen LU
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Publication number: 20230386547Abstract: A refresh address generation circuit includes: a refresh control circuit and an address generator. The refresh control circuit receives multiple first refresh commands in sequence and performs multiple first refresh operations accordingly, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operation is equal to m. The address generator is coupled to the refresh control circuit, and configured to prestore a first address and receive the first clock signal or the second clock signal, and during each first refresh operation, output an address to be refreshed in response to the first clock signal and change the first address in response to the second clock signal. The address to be refreshed includes a first address and a second address with the lowest bit opposite to that of the first address.Type: ApplicationFiled: January 11, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yinchuan GU
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Publication number: 20230389273Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate and an active pillar located above the substrate. The active pillar extends in a first direction. The first direction is parallel to a plane where the substrate is located. The active pillar includes a body area extending in the first direction and a peripheral area surrounding the body area. The peripheral area includes a channel area. A type of doped ions of the channel area is the same as a type of doped ions of the body area, and a doping concentration of the channel area is greater than a doping concentration of the body area.Type: ApplicationFiled: August 3, 2022Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jianfeng XIAO, Yi Tang
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Publication number: 20230386589Abstract: An anti-fuse structure includes: a first unit including a first selection transistor, a first anti-fuse (AF) cell and a second AF cell; and a second unit including a second selection transistor, a third AF cell and a fourth AF cell. The first unit and second unit share an active region, which is provided with a first extension part and a second extension part which are independent of each other at a first side, and provided with a third extension part and a fourth extension part which are independent of each other at a second side, the first side being opposite to the second side. The first AF cell is arranged at the first extension part, the second AF cell is arranged at the second extension part, the third AF cell is arranged at the third extension part, and the fourth AF cell is arranged at the fourth extension part.Type: ApplicationFiled: September 5, 2022Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Chuangming HOU
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Publication number: 20230386557Abstract: A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock processing circuit, configured to perform two-stage sampling and logical operation on the to-be-processed chip select signal according to a first clock signal to obtain a chip select clock signal; a chip select control circuit, configured to perform sampling on the to-be-processed chip select signal according to the first clock signal to obtain an intermediate chip select signal, and perform logical operations on the intermediate chip select signal, the to-be-processed chip select signal and the to-be-processed command signal to obtain a command decoding signal; and an output sampling circuit, configured to perform sampling on the command decoding signal according to the chip select clock signal to obtain a target command signal.Type: ApplicationFiled: August 11, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zequn HUANG
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Publication number: 20230386892Abstract: A semiconductor structure is formed by: providing a substrate, wherein an insulation layer, an initial metal conductive layer, an initial sacrifice layer, and a mask layer stacking in sequence are formed on the substrate, wherein the initial sacrifice layer includes a metal oxide layer; forming a metal conductive layer and a sacrifice layer atop the metal conductive layer by etching the initial sacrifice layer and the initial metal conductive layer using an oxygen source gas as an etching gas based on a patterned mask layer; removing the patterned mask layer by performing an ashing process using the oxygen source gas as the etching gas; removing the sacrifice layer as well as a by-product formed during the etching and the ashing process and exposing the metal conductive layer by performing a corrosion process using an alkaline corrosion solution; and forming an isolation structure between adjacent metal conductive layers.Type: ApplicationFiled: February 9, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Peimeng WANG, Ning XI, SHIJIE BAI
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Publication number: 20230389294Abstract: A transistor includes: a substrate including an active area; a gate structure penetrating through the active area and including a gate and a gate dielectric layer, in which the gate dielectric layer covers sidewalls and a bottom of the gate; a channel layer located on a side of the gate dielectric layer away from the gate, in which the channel layer includes a metal oxide semiconductor layer, in which the active area includes a first active layer and a second active layer located at two sides of the gate structure, and the first active layer and the second active layer are in contact with the channel layer.Type: ApplicationFiled: January 7, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: CHUN-WEI LIAO, Xiaoguang WANG, Deyuan XIAO, TZUNG-HAN LEE
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Publication number: 20230386546Abstract: A refresh address generation circuit includes: a refresh control circuit configured to sequentially receive first refresh commands and perform first refresh operations respectively, output a first clock signal when the number of the first refresh operations is less than a preset value or output a second clock signal when the number of the first refresh operations is equal to the preset value n, where n is a positive integer greater than or equal to 1; an address generator coupled to refresh control circuit, pre-storing a first address, receiving the first clock signal or the second clock signal, outputting a first to-be-refreshed address in response to the first clock signal during each first refresh operation, the first to-be-refreshed address includes the first address, and changing the first address in response to the second clock signal.Type: ApplicationFiled: June 9, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yinchuan GU
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Publication number: 20230389261Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a switching transistor and a storage transistor. The switching transistor includes a first gate electrode, a first channel layer coating a portion of the first gate electrode, and a first source-drain electrode and a second source-drain electrode both covering a surface of the first channel layer. The storage transistor includes a second gate electrode, a second channel layer coating a portion of the second gate electrode, and a third source-drain electrode and a fourth source-drain electrode both covering a surface of the second channel layer. A portion of the second gate electrode extending out of the second channel layer in a first direction is electrically connected to the second source-drain electrode. The storage transistor is configured to store charge.Type: ApplicationFiled: February 1, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: YOUMING LIU
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Publication number: 20230389288Abstract: A semiconductor structure includes a storage chip, a control chip, and a capacitor structure. The storage chip includes an array area. The control chip includes a peripheral area. The control chip and the storage chip are connected in a face-to-face bonding manner. The capacitor structure is located on a surface, away from a bonding surface, of the storage chip. The capacitor structure includes capacitors electrically connected to corresponding transistors in the array area.Type: ApplicationFiled: January 6, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Kanyu CAO, Tzung-Han LEE, Chih-Cheng LIU, Huaiwei YANG