Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
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Publication number: 20230386549Abstract: A refresh control circuit includes: a processing circuit, configured to receive a refresh command signal, and perform pulse combination processing on the refresh command signal to obtain a refresh combined signal, the refresh command signal having a plurality of pulses in a first time period and keeping a level state unchanged in a second time period, and the first time period and the second time period existing alternately; a logic circuit, configured to receive the refresh command signal and the refresh combined signal, and perform logical operation processing on the refresh command signal and the refresh combined signal to obtain a target control signal; and a power supply circuit, configured to receive the target control signal, and determine whether to perform a power supply operation according to the level state of the target control signal.Type: ApplicationFiled: January 20, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Liang ZHANG
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Publication number: 20230386599Abstract: A circuit for calibration control includes an off-chip calibration circuit and a mode switching circuit, and the off-chip calibration circuit includes a preprocessing circuit and a mapping circuit. The preprocessing circuit is configured to receive a current set of environmental parameters, decode the current set of environmental parameters and output parameter decoding signals. The mapping circuit is configured to receive the parameter decoding signals and output a first calibration code according to the parameter decoding signals. The mode switching circuit is configured to receive a calibration mode signal and the first calibration code, and determine the first calibration code as a ZQ calibration code in a case where the calibration mode signal indicates an off-chip calibration mode.Type: ApplicationFiled: August 11, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Kai TIAN
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Publication number: 20230386540Abstract: A timing sequence control circuit includes: a signal transmission module and a timing sequence compensation module, and the timing sequence compensation module is connected with the signal transmission module. Herein, the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal. The timing sequence compensation module at least includes a compensation capacitor and is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that the time difference between the sampling signal and a to-be-sampled Data (DQ) signal meets a preset requirement.Type: ApplicationFiled: February 14, 2023Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Kangling JI
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Publication number: 20230385169Abstract: A method and apparatus for testing a command are provided. The method includes that: when the test platform exists a target command to be sent to a memory, a duration of a deselect command is determined according to a minimum time interval between a target command and each of historical commands and the time when the each of the historical commands is sent and the present time; the target command is sent to the memory after the deselect command.Type: ApplicationFiled: August 30, 2022Publication date: November 30, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yu LI, Teng SHI
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Patent number: 11830750Abstract: A storage apparatus, and a transporting device and a transporting method for a Front Opening Unified Pod (FOUP) are provided. The storage apparatus includes: at least two carrying bins configured to carry the FOUP; and a rotating component. The at least two carrying bins are connected to the rotating component at different positions of the rotating component. The rotating component is configured to change positions of the at least two carrying bins through rotation of the rotating component.Type: GrantFiled: November 1, 2021Date of Patent: November 28, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Tianzhu Chen
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Patent number: 11830553Abstract: The application provides a Word Line (WL) drive circuit and a Dynamic Random Access Memory (DRAM). The WL drive circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. A gate of the first transistor is connected to a WL switch-off voltage, a drain is connected to the WL; a gate of the second transistor is connected to a first drive voltage of the WL, a drain is connected to the WL; and a source of the first transistor and a source of the second transistor are both connected to a negative bias through the third transistor.Type: GrantFiled: August 26, 2021Date of Patent: November 28, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Cheng-Jer Yang
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Patent number: 11830577Abstract: A First In First Out (FIFO) memory includes storage units. Outputs of the storage units are connected to one node. The storage unit includes storage sub-units, a selector, and a drive. An input of the selector is connected to outputs of the storage sub-units. An input of the drive is connected to an output of the selector. Driven by a first pointer signal, the storage sub-units receive storage data. Driven by a second pointer signal, the drive outputs the storage data.Type: GrantFiled: September 6, 2021Date of Patent: November 28, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Enpeng Gao
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Patent number: 11830702Abstract: Embodiments of the present disclosure provide a grid structure. The grid structure includes a carrier and a support column; wherein the support column is located on the carrier, the support column has a top surface for supporting a sample; and the support column has a groove, the groove extends along a direction from the top surface to the carrier, and a groove wall of the groove is connected to the top surface.Type: GrantFiled: June 30, 2021Date of Patent: November 28, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Wei Yang
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Patent number: 11830569Abstract: The present disclosure provides a readout circuit, a memory, and a method of reading out data of a memory. The readout circuit includes: a sense amplifier and an isolation unit, the sense amplifier being connected to a bit line and a complementary bit line through the isolation unit, the bit line being connected to a memory cell and the complementary bit line being connected to a memory cell, and the isolation unit being configured to disconnect the sense amplifier from the bit line and the complementary bit line in response to an isolation signal; and an offset canceling unit, configured to perform an offset cancellation on the sense amplifier in response to an offset canceling signal, at least a part of a stage of a charge sharing being performed at the same time as at least a part of a stage of an operation of the offset canceling unit.Type: GrantFiled: January 12, 2023Date of Patent: November 28, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Sungsoo Chi
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Publication number: 20230378956Abstract: A delay circuit includes a self-shielding circuit and a delay. The self-shielding circuit is configured to: receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal among the N initial clock signals that triggers the initial command signal at earliest, shield other N?1 second initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2, and the N initial clock signals have a same frequency and different phases. The delay is electrically connected to the self-shielding circuit and is configured to: receive the N intermediate command signals and the N initial clock signals, and delay and output the N intermediate command signals to obtain a delayed command signal. Thus, the accuracy of signal processing can be improved.Type: ApplicationFiled: January 17, 2023Publication date: November 23, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Tianchen LU
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Publication number: 20230378959Abstract: A counter circuit includes multiple stages of counting circuits corresponding to binary bits, each stage being configured to: obtain a carry signal and a this-time bit value according to an addend signal and a bit value currently output by the stage, output the carry signal to a next-stage counting circuit, latch the this-time bit value in response to a first clock and output same to an output terminal of the stage of counting circuit in response to a second clock. An output of the counter circuit is composed of bit values output by the multiple stages and is a binary representation of a counting result. An addend signal of a start-stage counting circuit is a high-level signal and an addend signal of a non-start-stage counting circuit is a carry signal output by an immediately previous stage. The first and second clocks are obtained based on division of a system clock.Type: ApplicationFiled: January 18, 2023Publication date: November 23, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yinchuan GU
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Publication number: 20230380134Abstract: Provided is a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, and a first gate structure and a first contact structure on the substrate, the first contact structure includes a first contact part and a second contact part, the first contact part is connected to the second contact part, the first contact part is located between the second contact part and the substrate, the first contact structure is electrically connected to the first gate structure and the substrate, and sectional area of the first contact part is greater than sectional area of the second contact part.Type: ApplicationFiled: March 13, 2023Publication date: November 23, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Min LI
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Publication number: 20230376061Abstract: A bandgap reference circuit includes a feedback transistor, a reference setting circuit, an amplification circuit and an output transistor. A source of the feedback transistor is configured to connect to a first power supply, and a drain of the feedback transistor is configured to connect to a first node. The reference setting circuit includes a first bridge arm and a second bridge arm which are connected in parallel. An inverting input terminal of the amplification circuit is connected to the first bridge arm, and a non-inverting input terminal of the amplification circuit is connected to the second bridge arm. A gate of the output transistor is connected to an output terminal of the amplification circuit, and a source of the output transistor is connected to the first power supply.Type: ApplicationFiled: September 30, 2022Publication date: November 23, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jianyong QIN
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Publication number: 20230375917Abstract: A method and a device for correcting a placement error of a photomask are provided. The method includes: acquiring an exposure offset during a wafer exposure after photomask manufacture is completed, wherein the wafer exposure is a process of forming a circuit pattern on a wafer surface by exposure; and determining a compensation offset for subsequent photomask manufacture according to the exposure offset, to correct a placement error of a photomask, wherein the compensation offset and the exposure offset are vector values that are equal in value and opposite in direction. The method and device for correcting the placement error of the photomask provided in the embodiments of the present disclosure can reduce an overlay error existing in a photolithography process of a semiconductor device by correcting a placement error of a photomask.Type: ApplicationFiled: August 13, 2021Publication date: November 23, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Xiuxuan ZHANG, Zhineng KONG
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Publication number: 20230376213Abstract: A method for hot swapping a memory includes the following: in response to a triggering operation of a replacement key of an abnormal memory, data on the abnormal memory is copied to an idle memory when a system is powered on; and the abnormal memory is powered off and replaced with a new memory after the data is copied; and in response to the triggering operation of a power on key of the new memory, the new memory is powered on. A method for hot swapping a memory in the case where a system is not powered off is provided.Type: ApplicationFiled: August 23, 2022Publication date: November 23, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Guowei HUANG
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Publication number: 20230377630Abstract: A sense amplifier includes a first power terminal, a second power terminal, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor. When the sense amplifier works, by outputting appropriate sequential logic signals to the four switching units respectively, controlling the on and off of the four switching units.Type: ApplicationFiled: June 30, 2021Publication date: November 23, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Weijie CHENG
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Patent number: 11825646Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following steps. A bit line structure is formed on a substrate. Each of the bit lines is provided with an insulation block on a side facing away from the substrate. A shielding portion is formed on a top of the insulation block that faces away from the substrate. A projection area of the shielding portion on the substrate is larger than a projection area of the insulation block on the substrate. An insulation sidewall is formed on a sidewall of the bit line and a sidewall of the insulation block, and a gap extending to the substrate is formed within the insulation sidewall corresponding to the shielding portion.Type: GrantFiled: October 12, 2021Date of Patent: November 21, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Bingyu Zhu, Jingwen Lu
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Patent number: 11821937Abstract: The embodiments of the present disclosure provide a semiconductor base plate and a test method thereof. When a first test line and a second test line in the semiconductor base plate are tested, a resistivity of the first test line can be tested by directly loading voltages to a first test pad and a second test pad after a first conductive layer is formed and before a first insulating layer is formed. After a second conductive layer is formed, a resistivity of the second test line is tested by loading voltages to a third test pad and a fourth test pad.Type: GrantFiled: January 12, 2022Date of Patent: November 21, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Qiang Li
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Patent number: 11823763Abstract: A sense amplifier includes: an amplification module, configured to amplify a voltage difference between a bit line and a reference bit line when the sense amplifier is in an amplification phase; a controllable power module, connected to the amplification module and configured to supply a first voltage to the amplification module when the sense amplifier is in a writing phase, and supply a second voltage to the amplification module when the sense amplifier is in a non-writing phase, and the second voltage is greater than the first voltage; and a writing module, connected to the bit line and the reference bit line and configured to pull the voltage difference between the bit line and the reference bit line according to to-be-written data when the sense amplifier is in the writing phase.Type: GrantFiled: September 30, 2021Date of Patent: November 21, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Hsin-Cheng Su
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Patent number: 11823765Abstract: The present application provides a storage system including a data port. The data port includes a data output unit. The data output unit includes: a pull-up unit having a control terminal, a first terminal and a second terminal, a first input signal being inputted to the control terminal, the first terminal being electrically connected to a power supply, the second terminal being connected to an output terminal of the data output unit, and the pull-up unit being a first NMOS transistor; and a pull-down unit having a control terminal, a first terminal and a second terminal, a second input signal being inputted to the control terminal, the first terminal being electrically connected to a ground terminal, and the second terminal being connected to the output terminal of the data output unit.Type: GrantFiled: February 5, 2021Date of Patent: November 21, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shuliang Ning
