Abstract: A three-dimensional memory and a method for forming the same are provided. The three-dimensional memory includes a substrate, a plurality of word lines and a plurality of lead lines. The word lines are located on the substrate. Each of the word lines extends in a first direction, and includes a first end and a second end opposite to the first end along the first direction. The lead lines are located on the substrate and are connected to the word lines in one-to-one correspondence. There are at least two adjacent word lines, in which the lead line connected to one of the at least two adjacent word lines is located at the first end, and the lead line connected to the other one of the at least two adjacent word lines is located at the second end.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; and forming a plurality of columns of stacked structures arranged at intervals in a first direction on the substrate, each stacked structures including a plurality of first sacrificial layers and a plurality of active layers that are stacked alternately. Part of each of the first sacrificial layers is removed to form a first trench and a second trench, and part of each of the active layers is exposed from the first trench and the second trench. Next, the exposed active layers are doped by ion doping to form first doped areas and second doped areas.

Abstract: Disclosed are a defect repair circuit and a defect repair method. The defect repair circuit includes: a test module, configured to perform defect test on a memory cell array in a test module to determine a defective memory cell, and output test address information and defect flag signal corresponding to the memory cell; a defect information storage module, connected with the test module, configured to store defect address information responsive to the defect flag signal, the defect address information being the test address information of the defective memory cell, and further configured to output first address information responsive to an externally input repair selection signal, the first address information being one of multiple pieces of defect address information; and a repair module, connected with the defect information storage module and configured to repair a corresponding defective memory cell according to the received first address information.

Abstract: A method for determining a sense boundary of a sense amplifier includes: writing first data into a memory array; reading the first data in a first memory cell of the memory array, and reversely writing second data into the first memory cell; reading, after a preset row precharge time, the first data in a second memory cell on a bit line where the first memory cell is located; and reversely writing the second data into the second memory cell when the first data is read in the second memory cell.

Abstract: A semiconductor structure includes a substrate, bit line structures, and capacitor connection lines. A plurality of bit line structures are arranged on the substrate. Contact holes are formed between adjacent bit line structures. A capacitor connection line includes a first conductive block and a second conductive block. The first conductive block and the second conductive block are sequentially filled in a contact hole. A chamfered structure is formed on a top end of the first conductive block. The chamfered structure is adjacent to a bit line structure. A bottom end of the second conductive block matches the chambered structure.

Abstract: Embodiments of the present disclosure provide a memory and its manufacturing method. The memory includes: a substrate with a plurality of mutually discrete bitlines, the bitline including a bitline conductive layer and a bitline insulating layer which are stacked in sequence; and an insulating layer and capacitor contact holes, the insulating layer being located on sidewalls of the bitline conductive layers and sidewalls of the bitline insulating layers, the capacitor contact holes being located between adjacent ones of the bitline conductive layers, sidewalls of the capacitor contact holes exposing the insulating layer, an opening size of the capacitor contact hole gradually increasing in a direction along the substrate and towards the insulating layer.

Abstract: The disclosure provides a data refreshing method of a memory, a controller of a memory, and a memory. The method includes that a target refreshing row in a data row of the memory is determined according to a running state of the controller, the target refreshing row including at least one data row; and in response to determining that a first refreshing interval expires and the target refreshing row includes a first reserved row, the first reserved row in the target refreshing row is refreshed. The first reserved row is a data row with data storage duration smaller than preset duration in the memory. The first refreshing interval is a refreshing interval of the first reserved row.

Abstract: A method for determining a Fail Bit (FB) repair scheme includes: a bank to be repaired of a chip to be repaired is determined, the bank to be repaired including multiple target repair areas; initial repair processing is performed on an FB in each of the target repair areas using a redundant circuit; responsive to that a number of remaining Redundant Word Lines (RWLs) is greater than 0 and a number of remaining Redundant Bit Lines (RBLs) is greater than 0, a candidate repair sub-scheme for each target repair area is determined, and a candidate repair cost corresponding to each candidate repair sub-scheme is determined; and a target repair scheme for the bank to be repaired is determined according to respective candidate repair sub-schemes and candidate repair costs, where the target repair scheme corresponds to a minimum integrated repair cost.

Abstract: A method and device for enhancing alignment performance of a lithographic device can provide an optimal alignment light source type to perform alignment according to product features. Overlay performance of the product can be improved, wafer reject can be reduced, and production efficiency can be enhanced.

Abstract: A manufacturing method of a semiconductor structure includes: providing a target layer; forming a plurality of first mask patterns on a top surface of the target layer; forming a plurality of second mask patterns above the target layer, where each of the second mask patterns covers at least a part of a top surface of each of the first mask patterns and a part of the top surface of the target layer in an extension direction of the second mask pattern; performing a first etching on the target layer based on the second mask patterns; removing the second mask patterns; and performing a second etching on the target layer based on the first mask patterns.

Abstract: A method for forming a memory device includes: after a hard mask layer is formed on a semiconductor substrate, a plurality of parallel mask patterns extending along a third direction are formed on the semiconductor substrate by adopting a self-alignment multi- pattern process, an opening is provided between the adjacent mask patterns, and the opening exposes surfaces of a plurality of drain regions and corresponding isolation layers in the third direction.

Abstract: The disclosure provides a sense amplifier and a control method thereof. The sense amplifier includes: a pre-charge module, a first input and output terminal, a second input and output terminal, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a first energy storage unit and a second energy storage unit. The sense amplifier can compensate for the offset voltage. The result is a sense amplifier with greatly reduced offset voltage, thereby improving the sensitivity and resolution of the sense amplifier.

Abstract: The present disclosure provides a method of manufacturing a semiconductor memory and a semiconductor memory, and relates to the technical field of storage devices. The method of manufacturing the semiconductor memory includes: providing a substrate, where multiple active regions arranged at intervals are provided in the substrate; each of the active regions includes a first contact region and second contact regions; forming a bump on each of the second contact regions; forming multiple bit line (BL) structures arranged at intervals on the substrate; forming a first isolation layer covering the BL structures and covering the substrate, where multiple filling holes are provided in the first isolation layer; and forming a wire in each of the filling holes, the wire being electrically connected to the bump.

Abstract: This application relates to a data transmission circuit, method, and storage devices. The comparison module compares the bus data on the data bus with the global data on the global data line, and the comparison result shows whether the number of bits that are different from the global data on the output bus data exceeds the preset threshold, which is set based on the comparison result. When the comparison result exceeds the preset threshold, a first data conversion module inverts the bus data and provides it to the data bus buffer module, and when the comparison result does not exceed the preset threshold, the bus data is provided to the data bus buffer module. The data bus buffer module generates a data polarity identification signal according to the comparison result, and transmit the bus data or the inverted data of the bus data to the global data line.

Abstract: The present invention provides an output driving circuit and a memory device. The output driving circuit is provided with a pull-up pre-amplification unit and a pull-down pre-amplification unit between a signal input terminal and a signal output terminal, the pull-up pre-amplification unit and the pull-down pre-amplification unit adjust the duty cycle ratios of the positive input signal and the negative input signal so that the duty cycle ratios of the output signals at the signal output terminal is the same as that of the input signal at the signal input terminal, which avoids the mismatch of output impedance under different output voltages, thereby eliminating the problem of duty cycle ratio deviation of the output signal that affects the signal quality.

Abstract: The present invention relates to an electrostatic protection circuit for protecting an internal circuit. The electrostatic protection circuit includes: a first circuit connected between a power pad and an input pad and configured to discharge a first electrostatic current; a second circuit connected between the input pad and a ground pad and configured to discharge a second electrostatic current; a third circuit connected between the power pad and the input pad and configured to discharge a third electrostatic current; a fourth circuit connected between the power pad and the ground pad and configured to discharge a fourth electrostatic current; a fifth circuit connected between the input pad and the ground pad and configured to discharge a fifth electrostatic current; and a sixth circuit connected between the ground pad and the power pad and configured to discharge a sixth electrostatic current.

Abstract: An error correction system includes M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y?Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate including a peripheral region, wherein the peripheral region includes a wire lead-out area, and the substrate is arranged with a plurality of discrete bit line structures; a dielectric layer formed between the adjacent bit line structures, wherein the peripheral region is arranged with a first contact hole; a wire lead-out area with a second through hole; a filling layer filling part of a first contact hole, wherein a remaining part of the first contact hole is defined as a first through hole; a first conductive layer located in the first through hole and the second through hole; and a conductive connecting wire located over the dielectric layer and being in contact with the first conductive layer in the wire lead-out area.

Abstract: Provided are a circuit for generating a bias signal and a clock input circuit for applying the circuit for generating a bias signal. The circuit for generating a bias signal includes: a first subcircuit, a first terminal of the first subcircuit being connected to a power supply voltage by means of a first node, a second terminal of the first subcircuit being connected to a current stabilization circuit by means of a second node, the first subcircuit being configured to generate a bias signal and output the bias signal by means of the second node, and the current stabilization circuit being configured to provide a constant current to the second node; and a second subcircuit, two terminals of the second subcircuit being respectively connected to the first node and the second node, the second subcircuit including a first resistor element and a first switch element connected in series.

Abstract: Provided are standby circuit dispatch method, apparatus, device and medium. The method includes: a first test item is executed and first test data is acquired, the first test data including position data of a failure bit acquired during execution of the first test item; a first redundant circuit dispatch result is determined according to the first test data; a second test item is executed and second test data is acquired; when the failure bit acquired during execution of the second test item includes a failure bit outside the repair range of the dispatched regional redundant circuits and dispatched global redundant circuits, and the dispatchable redundant circuits have been dispatched out, a maximum target bit umber is acquired according to the first test data and the second test data; and a target dispatch mode is selected and a second redundant circuit dispatch result is determined according to the target dispatch mode.