Abstract: A method for detecting a gas tightness of a furnace tube device includes: providing a test wafer; conveying the test wafer into the furnace tube device; depositing a dielectric layer on the test wafer; measuring a thickness and a Goodness of Fit (GOF) of the dielectric layer formed on the test wafer by a thickness measuring machine; and judging the gas tightness of the furnace tube device according to the GOF.

Abstract: A manufacturing method of a semiconductor structure includes: providing a target layer; forming a plurality of first mask patterns on a top surface of the target layer; forming a plurality of second mask patterns above the target layer, where each of the second mask patterns covers at least a part of a top surface of each of the first mask patterns and a part of the top surface of the target layer in an extension direction of the second mask pattern; performing a first etching on the target layer based on the second mask patterns; removing the second mask patterns; and performing a second etching on the target layer based on the first mask patterns.

Abstract: A method and device for Fail Bit (FB) repairing. The method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on first FBs in each target repair bank using a redundant circuit; second FBs are determined, and second repair processing is performed on the second FBs through a state judgment repair operation; for each target repair bank, unrepaired FBs in the target repair bank is determined, and candidate repair combinations and candidate repair costs of the unrepaired FBs are determined using an optimal combined detection manner; and a target repair cost is determined according to the candidate repair costs, and a target repair solution corresponding to the target repair cost is determined to perform repair processing on the unrepaired FBs according to the target repair solution.

Abstract: The embodiments relate to a semiconductor structure and a fabrication method thereof. The fabrication method includes: providing a wafer, in the wafer there being provided with a scribe line, in the scribe line there being provided with a test pad, a first test structure, and a second test structure; the second test structure being positioned below the first test structure, and a transverse pitch between the second test structure and the first test structure being at least equal to a width of the test pad; forming a protective layer on the wafer, the protective layer at least covering the scribe line; and performing exposure and development on the protective layer, such that a thickness of the protective layer remained above the first test structure is greater than that of the protective layer remained above the second test structure.

Abstract: A semiconductor structure includes a substrate and a conductive structure located above the substrate. The conductive structure includes a plurality of first conductive structures and second conductive structures that are spaced apart from each other and extend in a first direction. Lengths of the first conductive structures and lengths of the second conductive structures vary in steps. The lengths of the plurality of first conductive structures and the lengths of the plurality of second conductive structures vary in steps. The first conductive structures and the second conductive structures form Word Lines (WLs).

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; patterning the substrate to form a substrate layer and a plurality of silicon pillars; forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars; forming an isolation structure on the oxide layer, gaps being provided between upper part of the isolation structure and the silicon pillars; forming a first conductive layer in the gaps; partially removing the isolation structure and retaining the isolation structure below the first conductive layer to form an isolation layer; and forming a dielectric layer and a second conductive layer on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars.

Abstract: A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.

Abstract: A semiconductor layout structure includes: active layers, each active layer including a first active area and a second active area arranged adjacent to the first active area, the first active area including first transistor areas spaced apart from each other, the second active area including second transistor areas spaced apart from each other; and gate layers, each gate layer being arranged above a respective active layer, and including at least one first gate structure extending along a first direction, and second gate structures spaced apart from each other in the first direction, and the at least one first gate structure and the second gate structures being arranged adjacent to each other, the at least one first gate structure corresponding to the first transistor areas, and each second gate structure corresponding to a second transistor area.

Abstract: A read-write conversion circuit includes: a read-write conversion module, performing a read-write operation in response to a read-write control signal to implement data transmission between each of a local data line, a local complementary data line, and a global data line, data signals of the local data line and data signals of the local complementary data line being opposite in phase during the read-write operation, and a control module, outputting a variable read-write control signal in response to a read-write speed configuration signal to control a speed of the read-write operation of the read-write conversion module to be variable.

Abstract: Embodiments provide method for forming a connecting pad. The method includes: providing a substrate; sequentially forming a conductive layer, a first pattern definition layer and a second pattern definition layer on a surface of the substrate; sequentially forming three groups of patterns intersecting with each other at 120° on the second pattern definition layer, an intersection portion of the three groups of patterns forming a hexagonal pattern definition structure on the second pattern definition layer; transferring the pattern definition structure downward, and etching away a portion of the first pattern definition layer, such that the remaining first pattern definition layer forms a columnar structure, wherein a bottom of the columnar structure is circular in shape under an action of an etching load effect; and etching the conductive layer by using the remaining first pattern definition layer as a mask, such that the remaining conductive layer forms a circular connecting pad.

Abstract: A manufacturing method of a capacitive structure includes: providing a semiconductor base; forming a first mask layer on the semiconductor base, the first mask layer having a plurality of first round hole patterns distributed uniformly; forming first openings distributed uniformly on the semiconductor base by etching based on the first round hole patterns; forming a second mask layer on one side, away from the semiconductor base, of the first openings, and forming a plurality of second patterns on the second mask layer; forming second openings distributed uniformly on the semiconductor base by etching based on the second patterns; and etching the first openings and the second openings to form capacitive holes, and depositing a lower electrode layer, a dielectric layer and an upper electrode layer within the capacitive holes to form the capacitive structure.

Abstract: A method for preparing a semiconductor sample with an etched pit suitable for microscope observation is provided, including that a semiconductor sample piece is provided, the semiconductor sample piece including a sacrificial layer and a supporting layer which are stacked, and a trench which penetrates through the sacrificial layer and the supporting layer to expose a pit on a surface of a bottom metal layer; the semiconductor sample piece is steeped by placing it in an etching solution to remove the sacrificial layer; an adhesive tape is pasted on the surface of the semiconductor sample piece after the sacrificial layer is removed; and the adhesive tape is torn to remove the supporting layer above the pit to expose the pit.

Abstract: A semiconductor structure includes: a substrate; a first dielectric layer, located on the substrate; and a pad structure, located on the first dielectric layer. The first dielectric layer has at least one support layer. The pad structure is located above the support layer. A material strength of the support layer is greater than a material strength of the first dielectric layer.

Abstract: Embodiments of the present application provide a squeezing device, a photoresist supply system, and a photoresist supply method. The squeezing device comprises: a base, configured to bear a photoresist bottle; a support rail, vertically arranged on the base; a squeezing structure, an end of the squeezing structure is movably arranged on the support rail so that the squeezing structure moves up and down along the rail direction of the support rail; and a driving module, configured to drive the squeezing structure to deform the squeezing structure so as to reduce the area of a region enclosed by the squeezing structure, and also configured to drive the deformed squeezing structure so that the squeezing structure moves up and down along the rail direction of the support rail. By squeezing the photoresist bottle by the squeezing device, the utilization rate of the photoresist in the photoresist bottle is improved.

Abstract: A circuit for transmitting data includes a mode register data processing module, an external data transmission module, and an internal data transmission module provided in a memory array; the mode register data processing module is configured to write initial data into a reserved mode register in a mode register in response to a write enable command; and the external data transmission module is electrically connected to both the reserved mode register and the internal data transmission module, and is configured to write, in response to an enable signal, target data into the memory array via the internal data transmission module according to the initial data and a preset encoding rule, wherein a number of bytes of the target data is greater than a number of bytes of the initial data.

Abstract: Disclosed in the embodiments of the disclosure are an anti-fuse address decoding circuit, an operation method, and a memory. The anti-fuse address decoding circuit includes: a pre-decoding circuit, configured to decode a programming address of an anti-fuse memory array and output a programming address pre-decoded signal; a level shift circuit, coupled to the pre-decoding circuit, and configured to boost the programming address pre-decoded signal and output a boosted signal; and a programming address decoding circuit, configured to receive the boosted signal, decode the boosted signal and output a programming address signal.

Abstract: A preprocessing module receives a word line activation command and a clock signal and outputs a word line address corresponding to a current word line activation command as a word line address signal when a count value reaches a preset value. An address processing module counts all received word line address signals and outputs a word line address signal with the largest number of occurrences as a row hammer address. A first processing unit generates first and second supplementary refresh address according to the row hammer address. A second processing unit generates a normal refresh address according to a refresh command. A refresh unit performs a refresh operation according to an acquired address signal. A control unit selects to output a refresh address or control the refresh unit to select to receive a refresh address.

Abstract: A comparator includes a first-stage circuit, a second-stage circuit, a first switching circuit and a second switching circuit. The first-stage circuit includes a first input circuit and a second input circuit. The first switching circuit is configured to control the conduction of the first input circuit, and the second switching circuit is configured to control the conduction of the second input circuit. The first input circuit is configured to generate a first differential signal in a sampling phase when being switched on. The second input circuit is configured to generate a second differential signal in a sampling phase when being switched on. The second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal.

Abstract: Provided are a Fail Bit (FB) repair solution determination method and device, which are applied to a chip including multiple subdomains. The chip further includes Redundancy (RD) circuits, and the RD circuits are configured to repair FBs in the subdomains. The method includes that: after one or more available RD circuits are determined for a target FB presently to be repaired in a subdomain, a reliability value of each available RD circuit is acquired from an RD circuit reliability list, the RD circuit reliability list including reliability values of multiple RD circuits, and a repair solution for the target FB in the subdomain is determined according to the reliability value of the available RD circuit. The reliability value of the RD circuit is obtained by performing big data analysis on relationships between generated FBs and RD circuits where NFBs are located in the RD circuits.

Abstract: Embodiments disclose a capacitor array structure and a method for fabricating a capacitor array structure. The method includes: after forming a first capacitor hole, providing a bonded wafer including a second substrate, a second supporting layer and a second sacrificial layer stacked in sequence, and bonding the bonded wafer to a stacked structure, wherein a surface of the second sacrificial layer away from the second supporting layer is a bonding surface; forming a second capacitor hole, the second capacitor hole penetrating into the bonded wafer at least along a thickness direction to expose the first capacitor hole, such that the first capacitor hole is connected with the second capacitor hole.