Abstract: A semiconductor structure includes a substrate, a barrier layer covering the substrate, first adjustment layers, and first contact structures. The substrate includes multiple spaced Active Areas (AAs). The AAs include first contact areas. The barrier layer is provided with multiple spaced first contact holes, each of which penetrates through the barrier layer and extends into the substrate to expose a respective one of the first contact areas. Each of the first adjustment layers is on a sidewall of a respective one of the first contact holes. Each of the first contact structures fills a respective region enclosed by the first adjustment layer and the first contact area. A method for manufacturing a semiconductor structure is also provided.

Abstract: In a method for forming a semiconductor device, a substrate is provided; a word line is formed in the substrate by taking a first face of the substrate as an upper surface; a connecting layer electrically connected to one end of the word line is formed in part of the substrate and on the substrate; a first conducting layer is formed on the connecting layer; and a conducting plug is formed in the substrate by taking a second face of the substrate as an upper surface. The conducting plug is electrically connected to another end of the word line and electrically connected to the first conducting layer via the word line. The first face and the second face are two faces of the substrate opposite to each other in a thickness direction of the substrate.

Abstract: A semiconductor structure includes a gate dielectric layer and a gate located on a surface of the gate dielectric layer, in which the gate dielectric layer includes an oxide layer, a charge trapping layer and an isolation layer stacked in sequence, and the isolation layer is made of a polarization material capable of spontaneous polarization.

Abstract: A circuit for through silicon via (TSV) detection includes a TSV to be tested, an equivalent adjustable resistor and a reverse output circuit. A first terminal of the TSV to be tested is connected to a second terminal of the equivalent adjustable resistor, and a second terminal of the TSV to be tested is grounded. An input terminal of the reverse output circuit is connected to the first terminal of the TSV to be tested. The method includes: adjusting a resistance value of the equivalent adjustable resistor to a preset first resistance value, and keeping a voltage of a first terminal of the equivalent adjustable resistor at a preset voltage value, the first resistance value is a maximum resistance value of an equivalent resistor corresponding to the TSV to be tested when the TSV to be tested is normal.

Abstract: A refresh circuit includes a refresh counter configured to output address signals through a plurality of address pins; an address mixer configured to output row address selection signals according to the address signals received by the row address pins, output first bank address signals according to the address signals received by bank address pins, receive a refresh signal and a power supply voltage signal, and output fixed second bank address signals according to the refresh signal and the power supply voltage signal; and an address pre-decoding circuit configured to output a preset number of bank address selection signals according to the first bank address signals and the second bank address signals.

Abstract: A circuit includes a delay generation circuit. The delay generation circuit is configured to generate a sub-grab signal for each of the storage areas based on an initial grab signal and data transmission delay of each of the storage areas, and generate a grab enable signal based on all the sub-grab signals. A time interval between a time when the read-write control circuit receives data transmitted from each of the storage areas by a global data line and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range. The read-write control circuit is configured to read out data of the global data line to a data bus based on the grab enable signal. Therefore, the tCCD of the DRAM is optimized.

Abstract: A data error correction circuit includes: a data error correction circuit, configured to receive first data and a first check code corresponding to the first data, perform error correction on the first data according to the first check code to generate second data, and output the second data; and a check code generation circuit, configured to receive the first data and the first check code, generate a second check code according to the first data and the first check code, and output the second check code.

Abstract: A method and device for data synchronization, a storage medium and an electronic device are provided. The method for data synchronization includes operations as follows. Synchronization configuration information for data to be synchronized is determined, and the synchronization configuration information at least includes a data identification of the data to be synchronized and a source data table identification of a source data table where the data to be synchronized is located. A source database is queried based on the source data table identification to obtain a target source data table where the data to be synchronized is located. A field identification of the data to be synchronized is determined from the target source data table based on the data identification. A target data table is constructed based on the field identification, and the data to be synchronized is synchronized into the target data table.

Abstract: The present disclosure provides a semiconductor device, and a capacitor device and its manufacture method, and relates to the field of semiconductor technologies. The manufacture method includes: forming, on a substrate, a plurality of storage node contact plugs distributed in an array and an insulation layer separating each of the storage node contact plugs; forming an electrode supporting structure on a side of the insulation layer away from the substrate, the electrode supporting structure having a plurality of through holes exposing each of the storage node contact plugs respectively, the through hole comprising a plurality of hole segments end-to-end jointing successively, the hole segment located on a side close to the substrate having an aperture greater than the hole segment located on a side away from the substrate; forming a dielectric layer; forming a second electrode layer.

Abstract: A method for manufacturing a semiconductor structure includes: forming multiple trenches spaced apart from each other and extending in a first direction in a substrate, and forming a first insulating layer on sidewalls and bottoms of the trenches; forming a first conductive layer on a surface of the first insulating layer; removing part of the first conductive layer to an initial depth by a first etching process; removing remaining part of the first conductive layer to a target depth by a second etching process.

Abstract: A manufacturing method for a test structure includes: providing a substrate, and forming a gate dielectric film and a conductive film being stacked successively on the substrate; patterned etching at least the conductive film to form a plurality of gate structures discretely located on the substrate, the distance between adjacent gate structures in an arrangement direction of the gate structure being less than or equal to 110 nm; forming isolation sidewalls on two opposite sides of the gate structures; and, implanting doping ions into the substrate to form doped regions by taking the gate structures and the isolation sidewalls as masks, the distance between the doping depth of the doped regions and the top surface of the substrate in a direction perpendicular to the surface of the substrate being less than 10 nm.

Abstract: A method and apparatus for intensifying current leakage between adjacent memory cells includes that: a write operation is performed on a memory array, to form a column strip test pattern, the column strip test pattern being formed by arranging low-level memory cells and high-level memory cells in columns, and N columns of high-level memory cells being present between two adjacent columns of low-level memory cells, N?2; and voltage adjustment is performed on the low-level memory cells and the high-level memory cells, to increase potential differences between the low-level memory cells and the high-level memory cells.

Abstract: A test structure and a test method are provided. The test structure includes: a first interdigital structure including first and second conductive comb tooth portions, where comb tooth ends of the second and first conductive comb tooth portions are arranged alternately in sequence and spaced apart and there is a first distance between the comb tooth ends of the second and first conductive comb tooth portions; and a second interdigital structure including third and fourth conductive comb tooth portions, where comb tooth ends of the fourth and third conductive comb tooth portions are arranged alternately in sequence and spaced apart; there is a second distance between the comb tooth ends of the fourth and third conductive comb tooth portions, which is not equal to the first distance; and the first and second conductive comb tooth portions are electrically connected to the third and fourth conductive comb tooth portions respectively.

Abstract: A semiconductor device includes: a semiconductor substrate and a memory cell located on a surface of the semiconductor substrate; the semiconductor substrate comprises a well area, an isolation structure, a first doped area and a second doped area; the isolation structure, the first doped area and the second doped area are located in the well area, and the isolation structure at least is located between the first doped area and the second doped area; the memory cell is located on a top surface of the second doped area and is electrically connected with the second doped area.

Abstract: A method for regulating the memory includes operations as follows. A mapping relationship among temperatures of a transistor, body bias voltages of the transistor, and data writing time of the memory is acquired, a current temperature of the transistor is acquired, the body bias voltage is regulated based on the current temperature and the mapping relationship, to enable the data writing time corresponding to the regulated body bias voltage to be within a preset writing time.

Abstract: The present disclosure in the field of memory technology proposes a programmable storage cell, a programmable storage array and a reading and writing method for the programmable storage array. The programmable storage cell includes: a first anti-fuse element connected between a first power terminal and an output terminal, a second anti-fuse element connected between the second power terminal and the output terminal, and a third switch unit connected to the output terminal, a third power terminal and a position signal terminal, where the third switch unit responds to the signal from the position signal terminal so as to connect the third power terminal and the output terminal. The programmable storage cell has a simple structure and a high reading speed.

Abstract: A method of preparing an air gap includes: forming a first covering layer etching and removing part higher than a horizontal line where a top of the oxide layer is located; forming a first oxide layer on an etched plane; etching the first oxide layer; removing a part of the first oxide layer; reserving a rest part of the first oxide layer; taking a reserved first oxide layer as an oxide layer pattern; forming a second covering layer at a position of a removed part of the first oxide layer; removing the oxide layer pattern and the oxide layer.

Abstract: A method, apparatus and device for determining production capacity boundaries are provided. In the method, related data for producing a run size of elements by a production device lot by lot is acquired and time intervals between production ending time points of adjacent lots are determined according to the related data; the determined time intervals are sorted to obtain a time interval sequence; distribution features of time intervals at two boundaries are parsed respectively to determine whether a data removing condition is satisfied; if Yes, an outlier is determined according to a mean value of the present time interval sequence, the time interval of the extraction step length where the outlier is located is removed, and whether the data removing condition is satisfied is determined; and if No, production capacity boundaries are determined according to minimum and maximum time intervals of the present time interval sequence and the run size.

Abstract: In a method for buffer insertion, a circuit to be processed and a plurality of insertion strategy parameters are determined; a target insertion strategy parameter is determined by calculating the plurality of insertion strategy parameters by using a preset population genetic model; and a target circuit is obtained by performing buffer insertion processing on the circuit to be processed according to the target insertion strategy parameter.

Abstract: A manufacturing method for a semiconductor structure includes: providing a substrate, where the substrate includes an array area and a peripheral area; the array area is provided with active area and first isolation structures; the peripheral area is provided with second isolation structures; and forming gate structures in the array area, and simultaneously forming resistor structures in the second isolation structures of the peripheral area by the step of forming the gate structures.