Abstract: A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming an MTJ structure and a first mask structure in sequence on the substrate; performing a patterning process on the first mask structure to form a first pattern extending in a first direction; transferring the first pattern to the MTJ structure; forming a second mask structure on the MTJ structure; performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction and being not perpendicular to the second direction; and performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.

Abstract: A semiconductor structure includes: a base, including a substrate, a first isolation layer, a first dielectric layer, and a stop layer that are formed in a stack manner, a first contact hole being formed in the base; a first insulating layer and a first barrier layer sequentially formed on an inner wall of the first contact hole, a first contact structure being disposed in the first contact hole; a protective layer covering an upper surface of the first contact structure; a second dielectric layer and a second isolation layer sequentially stacked on the protective layer, a second contact hole being formed in the base; and a second barrier layer formed on an inner wall of the second contact hole and a second contact structure disposed in the second contact hole.

Abstract: The present disclosure provides a method of forming a capacitor array and a semiconductor structure. The method of forming a capacitor array includes: providing a substrate, the substrate including an array region and a non-array region, wherein a base layer and a dielectric layer are formed in the substrate, and a first barrier layer is formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of each of the first array definition layer and the second array definition layer; patterning the dielectric layer and the second array definition layer by using the pattern transfer layer as a mask, and forming a capacitor array located in the array region.

Abstract: The present disclosure provides a method for detecting a memory and a device for detecting a memory. The memory includes first memory cells, second memory cells, bit lines, complementary bit lines, word lines, and a plurality of sense amplifiers, where each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; and the method includes: writing storage data into each of the first memory cells and each of the second memory cells; performing a read operation; obtaining a test result based on a difference between real data and the storage data; and obtaining a leakage position of the bit line and the word line or a leakage position the complementary bit line and the word line based on the test result.

Abstract: An equalizer circuit, a method for sampling data and a memory are provided. The equalizer circuit includes a first input buffer circuit, a second input buffer circuit and a selecting and sampling circuit. The first input buffer circuit and the second input buffer circuit are respectively connected with the selecting and sampling circuit, and reference voltages used in the first input buffer circuit and the second input buffer circuit are different from each other. The selecting and sampling circuit selects to perform data sampling on a data signal outputted by the first input buffer circuit or the second input buffer circuit according to data outputted previously by the equalizer circuit, and takes sampled data as data outputted currently by the equalizer circuit.

Abstract: The water storage device includes: a water storage cavity and a water inlet, the water inlet being configured to feed a solution into the water storage cavity, the water storage cavity being configured to store or discharge the solution and containing a viscous substance; a guide rod and a floating device movable along the guide rod, the floating device being movable as a water level in the water storage cavity changes, and the viscous substance between the guide rod and the floating device restraining movement of the floating device; and a water curtain casing, the water curtain casing being connected to the water inlet and configured to split a part of the solution from the solution fed from the water inlet, and the solution split by the water curtain casing being configured to flush the viscous substance between the guide rod and the floating device.

Abstract: A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.

Abstract: A DRC test pattern generation method includes: receiving a DRC test pattern generation request, the DRC test pattern generation request carrying the number of correct patterns and the number of erroneous patterns; acquiring layout design rule information and corresponding layer configuration information, the layer configuration information including process layer configuration parameter information that is set according to a process type; parsing parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the layer configuration information, and generating formatted parameter information corresponding to the each rule; and generating a corresponding number of correct patterns and a corresponding number of erroneous patterns corresponding to each rule according to the formatted parameter information.

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; in which the bit line isolation trenches extend in a second direction, the first direction being perpendicular to the second direction; forming a bit line isolation layer in a bit line isolation trench; in which a gap is provided between the bit line isolation layer and the bit line isolation trench, in which the gap is located at a bottom corner of the bit line isolation trench and extends in the second direction, and exposes part of the bottom of the bit line isolation trench; etching a first semiconductor pillar in the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.

Abstract: A manufacturing method of a semiconductor structure includes the following operations. A substrate is provided, which includes a first N region, a first P region, a second N region and a second P region adjacently arranged in sequence. A gate dielectric layer, a first barrier layer, a first work function layer and a second barrier layer are formed on the substrate in sequence. A mask layer is formed on the second barrier layer of the first P region and the second P region. The second barrier layer of the first N region and the second N region is removed by a first etching process with the mask layer as a mask. The first work function layer and the first barrier layer of the first N region and the second N region are removed by a second etching process. A semiconductor structure is also provided.

Abstract: A transistor comprises a substrate; a gate trench located in the substrate; a first gate layer located in the gate trench, and a material of the first gate layer comprising TiN or comprising W; a second gate layer located in the gate trench and covering the first gate layer, a material of the second gate layer comprising TiNx, wherein 0 ? x< 1, and a work function of the second gate layer being smaller than a work function of the first gate layer.

Abstract: A fuse fault repair circuit includes a fuse array, a signal storage module, and a scan repair module. The fuse array includes a redundant fuse array and a non-redundant fuse array. When the fuse array is not faulty, the redundant fuse array has no signal output, and the non-redundant fuse array outputs S first logic signals. Each storage unit in the signal storage module is configured to store a first logic signal sent by one fuse unit connected thereto. The scan repair module is configured to scan the storage units in the signal storage module, determine, when a faulty storage unit is scanned, that a first fuse unit connected to the faulty storage unit is faulty, and replace the first fuse unit with a first redundant fuse unit corresponding to the first fuse unit. The first logic signal corresponding to the first redundant fuse unit is a normal signal.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a semiconductor substrate, and forming a first bit line; forming a support layer on the semiconductor substrate, the support layer including a first oxide layer, a first sacrificial layer, a second oxide layer, a second sacrificial layer, a third oxide layer, a third sacrificial layer and a fourth oxide layer that are stacked; forming, at a position corresponding to the first bit line, an active pillar penetrating through the support layer; removing each of the first sacrificial layer and the third sacrificial layer, and forming a first trench; removing a peripheral wall of the active pillar to form a first annular groove, a size of the first annular groove being greater than a size of the first trench in a vertical direction; forming a P-type filler in the first annular groove.

Abstract: A semiconductor device includes a semiconductor substrate, a word line trench and a word line structure. The word line trench includes a first word line trench and a second word line trench. The word line structure includes a first word line structure part and a second word line structure part connected to each other. The first word line structure part is formed in the first word line trench, and the second word line structure part is formed in the second word line trench; and the first word line structure part includes an avoidance region, and the top surface of the avoidance region is aligned with the top surface of the second word line structure part, and the avoidance region is provided with insulating material.

Abstract: Disclosed is a method for manufacturing a semiconductor device. The method includes: forming a gate insulating material layer on a substrate; forming a gate material layer on the gate insulating material layer; and performing an etching process on the gate material layer and the gate insulating material layer to form a gate layer and a gate insulating layer. The gate insulating layer and the gate layer each include a first end and a second end opposite to each other in a direction parallel to a channel length. The first end of the gate insulating layer is recessed inwards by a preset length relative to the first end of the gate layer, and the second end of the gate insulating layer is recessed inwards by the preset length relative to the second end of the gate layer.

Abstract: A semiconductor structure includes the following: a semiconductor substrate; a first metal layer, located on a surface of the semiconductor substrate; a second metal layer, located above a surface of the first metal layer; an insulating layer, located between the first metal layer and the second metal layer, and configured to isolate the first metal layer and the second metal layer; a test via, penetrating through the insulating layer and connecting the first metal layer with the second metal layer through a conductive material in the test via; and at least a pair of dummy vias, penetrating through the insulating layer and connected to any one of the first metal layer and the second metal layer.

Abstract: A method for manufacturing a shallow trench isolation structure includes: providing a substrate and forming multiple first trenches in the substrate, in which a cross-sectional width of each first trench increases downward along a vertical direction; forming a continuous first isolation layer on a top of the substrate and inner sides of the multiple first trenches by a deposition process, in which parts of the first isolation layer located in the first trenches form second trenches, and in which a cross-sectional width of each second trench remains constant downward along the vertical direction; and forming a continuous second isolation layer on a surface of the first isolation layer by an ISSG process, in which parts of the second isolation layer located in the second trenches completely fill up the second trenches.

Abstract: The present application relates to a semiconductor memory training method and related devices, belonging to the technical field of semiconductors. The method comprises: obtaining a stored historical training result of a semiconductor memory, the historical training result comprising a historical expected delay value and a historical expected voltage; setting a delay threshold and a current training voltage range, the delay threshold being less than or equal to the historical expected delay value, the current training voltage range comprising the historical expected voltage; obtaining a current minimum delay value for the semiconductor memory under the historical expected voltage; and using the stored historical training result as a current training result of the semiconductor memory, if the current minimum delay value for the semiconductor memory under the historical expected voltage is no less than the delay threshold.

Abstract: The present disclosure relates to the field of semiconductor packaging processes, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with an exposed conductive structure; forming a passivation layer on the surface of the semiconductor substrate and a surface of the exposed conductive structure; etching the passivation layer to form a recess, where a bottom of the recess exposes one end of the conductive structure; forming an adhesion layer on a surface of the recess; and etching to form a hole in the bottom of the recess.

Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor wafer, and acquiring surface flatness information of the semiconductor wafer; determining an exposure parameter of the semiconductor wafer according to the surface flatness information of the semiconductor wafer; and exposing the semiconductor wafer according to the exposure parameter.