Abstract: A signal output circuit and a circuit for outputting a delayed signal are provided. The signal output circuit includes: a first control subcircuit, configured to receive a first pulse signal and an input signal and output a first adjustment signal, a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal; a second control subcircuit configured to receive a second pulse signal and the input signal and output a second adjustment signal; and the signal output subcircuit is configured to receive the first adjustment signal and the second adjustment signal, and output a delayed output signal, a rising edge of the delayed output signal is generated according to the first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated according to the second preset edge of the second adjustment signal.

Abstract: The embodiments provide a detection circuit and a detection method. The detection circuit includes an ESD protection device, a first fuse and a transistor. A first terminal of the ESD protection device is connected to a first terminal of the first fuse, and a connection terminal of the ESD protection device and the first fuse serves as a first test terminal; a second terminal of the first fuse is connected to a gate electrode of the transistor, and a connection terminal of the first fuse and the transistor serves as a second test terminal; and a second terminal of the ESD protection device is connected to at least one of a source electrode, drain electrode or substrate of the transistor, and a connection terminal of the ESD protection device and the transistor serves as a third test terminal.

Abstract: A test board for testing a memory signal includes a first surface and a second surface. The first surface of the test board comprises a convex region and a non-convex region. The convex region is provided with a first connection area connectable to a main board, and a level at which the convex region is located is higher than a level at which the non-convex region is located by a preset value. The second surface of the test board includes a test area and a second connection area connectable to a memory chip. The test board is provided with a first connection harness for connecting the test area to the first connection area and a second connection harness for connecting the test area to the second connection area, to enable the memory signal of the memory chip to be tested based on the test area.

Abstract: A semiconductor structure and a forming method thereof are provided. The method for forming a semiconductor structure includes providing a base including a semiconductor substrate and a well region located on a surface of the semiconductor substrate, in which the well region includes a plurality of active pillar columns arranged at intervals along a first direction, and each of the active pillar columns includes a plurality of active pillars arranged at intervals along a second direction, in which the first direction is perpendicular to the second direction; forming a plurality of bit line trenches by etching at least the well region and a partial thickness of the semiconductor substrate at bottoms of the active pillars; and forming buried bit lines in the bit line trenches.

Abstract: A failure pattern obtaining method and apparatus are provided. The method includes that: a chip test result picture for a wafer is obtained, the chip test result picture being marked with a plurality of failure test points; a vector for every two points among all failure test points is calculated; a plurality of failure test points having a same vector are designated as a same group; a plurality of pending failure patterns are separated from each of groups; a failure pattern is obtained based on the plurality of the pending failure patterns.

Abstract: Embodiments of the present disclosure provide a memory detection method and detection apparatus, for detecting a current-leakage bitline. The method includes: a memory including a plurality of memory cells, a plurality of sense amplifiers, and the sense amplifier including a power line providing a low potential voltage and a power line providing a high potential voltage; writing first memory data to each of the memory cells; performing a reading operation after the first memory data is written; acquiring a first test result based on a difference between first real data and the first memory data; performing the reading operation again to read second real data in each of the memory cells; acquiring a second test result based on a difference between the second real data and second memory data; and acquiring a specific position of the current-leakage bitline based on the second test result and the first test result.

Abstract: The present disclosure provides a mounting fixture of a bearing ring for a wafer. The bearing ring includes a circular ring portion, screw elements, and multiple permanent seats, wherein the circular ring portion includes a ring body and multiple lugs provided with light holes, each of the permanent seats is provided with a threaded hole, and one of the screw elements can be in threaded connection with the threaded hole after passing through a light hole. The mounting fixture includes a first clamp body and a second clamp body, where the first clamp body is provided with a first circular hole portion and first groove portions; a diameter of the first circular hole portion is greater than or equal to an external diameter of the ring body; the second clamp body is provided with second groove portions penetrating through the second clamp body.

Abstract: The present disclosure provides an antifuse array structure and a memory. The antifuse array structure includes a plurality of antifuse integrated structures arranged in a bit line extension direction and a word line extension direction to form an antifuse matrix. The antifuse integrated structure is arranged in a same active region, and an extension direction of the active region is the same as the bit line extension direction. Each antifuse integrated structure includes a first antifuse memory MOS transistor, a first switch transistor, a second switch transistor, and a second antifuse memory MOS transistor. The first switch transistor and the second switch transistor are respectively controlled through two adjacent word lines, the first antifuse memory MOS transistor and the second antifuse memory MOS transistor are respectively controlled through two adjacent programming wires, and the programming wire is further configured to control adjacent antifuse integrated structures.

Abstract: A semiconductor structure includes: a through silicon via penetrating a base; and a protection structure, including: a conductive first test ring and a conductive second test ring both arranged around the through silicon via and electrically insulated from the through silicon via; a first dielectric layer located between the first test ring and the second test ring and configured to electrically isolate the first test ring from the second test ring; and a first connection layer located in the first dielectric layer and configured to be electrically connected to the first test ring and the second test ring.

Abstract: A signal masking circuit includes a receiving circuit, a delay control circuit, and a logical operation circuit. The receiving circuit is configured to: receive a signal to be processed and a chip select (CS) signal, and output an initial processing signal and an initial CS signal. The delay control circuit is configured to perform delay and logical control operations on the initial CS signal to obtain a CS masking signal, where a pulse width of the CS masking signal is greater than or equal to two preset clock periods. The logical operation circuit is configured to perform invalid masking on the initial processing signal according to the CS masking signal to obtain a target signal.

Abstract: Embodiments provide a method for forming a semiconductor structure and the semiconductor structure. The method includes: providing a base including bit line trenches extending in a first direction and arranged in a second direction; forming a bit line structure in each bit line trench; and etching the base with bit line structures formed therein to form active areas corresponding to the bit line structures. Each column of the active areas arranged in the first direction includes the active areas extending in a third direction, and the first direction, the second direction and the third direction are positioned in a same plane, and there is a first preset included angle between the second direction and the first direction and a second preset included angle between the third direction and the first direction.

Abstract: A method for manufacturing a semiconductor structure includes operations as follows. First mask pattern layers spaced apart on a base are formed. A first dielectric layer is deposited between the first mask pattern layers. The first dielectric layer is etched to form a first trench, the first trench exposing the base and a part of side walls of the first mask pattern layers. The base is etched to a first depth along the first trench, to expose the base under the first mask pattern layers. The base under the first mask pattern layers is etched to form gaps in the base.

Abstract: The present disclosure provides a test method and a test apparatus for a semiconductor device. The test method includes: forming a plurality of test values based on a first retention time range and a first step size, and sequentially testing a plurality of memory cells in the semiconductor device based on the plurality of test values in ascending order; determining, during tests corresponding to each test value, a memory cell whose retention time is less than the test value, and recording a position and corresponding test value of the memory cell whose retention time is less than the test value, to form first test data; a similar method is applied to form second test data; and determining, based on the first test data and the second test data, positions and corresponding test values of memory cells whose retention times fail to pass the tests.

Abstract: A semiconductor structure includes a semiconductor substrate, a trench being provided in the semiconductor substrate, and a gate being formed in the trench; an ion implantation layer located in the semiconductor substrate outside the trench, a top surface of the ion implantation layer being higher than that of the gate, and a bottom surface of the ion implantation layer being lower than the top surface of the gate and higher than a bottom surface of the gate; a transition layer located between the gate and the ion implantation layer, a bottom surface of the transition layer being lower than the top surface of the gate and higher than the bottom surface of the gate, and a doping concentration of the transition layer being lower than that of the ion implantation layer.

Abstract: A semiconductor structure includes: a semiconductor substrate, in which a trench is provided in the semiconductor substrate, and a gate is formed in the trench; and a doped layer, in which the doped layer is located in the semiconductor substrate on an outer side of the trench. In a direction perpendicular to the semiconductor substrate, the doped layer includes a transition layer and an ion implantation layer located on the transition layer. A doping concentration of the transition layer is less than a doping concentration of the ion implantation layer; and in the direction perpendicular to the semiconductor substrate, a top surface of the transition layer is not lower than a bottom surface of the gate.

Abstract: An error correction system is disclosed. The error correction system is applied to a storage system. The error correction system generates X first operation codes, Y second operation codes and a third operation code based on the storage system. The error correction system includes an error state determining circuit and M decoding circuits. The error state determining circuit is configured to identify a current error state. When a plurality of pieces of data have a 1-bit error, the M decoding circuits are configured to execute decoding processing on the X first operation codes and the Y second operation codes, to obtain whether there is erroneous data in the bytes corresponding to the decoding circuits and locate a bit to which the erroneous data belongs.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; bit lines, located on the base, and a material of the bit line including a metal semiconductor compound; semiconductor channels, each including a first doped region, a channel region and a second doped region arranged in sequence, and the first doped region being in contact with the bit line; a first dielectric layer, covering sidewall surfaces of the first doped regions, and a first interval being provided between parts of the first dielectric layer covering sidewalls of adjacent first doped regions on a same bit line; an insulating layer, covering sidewall surfaces of the channel regions; word lines, covering a sidewall surface of the insulating layer away from the channel regions, and a second interval being provided between adjacent word lines.

Abstract: Provide are a reticle transfer device and an exposure system. The reticle transfer device includes a bearing member, a light source, a light detector and a controller. The bearing member is configured to bear the reticle, and the light source is configured to emit irradiation light to the reticle and form reflected light. The light detector is configured to obtain the reflected light and generate a light detection signal. The controller is configured to determine whether particulate matter exists on a surface of the reticle based on the light detection signal. The reticle transfer device can determine whether particulate matter exists on the surface of the reticle in real time based on the light detection signal.

Abstract: The present disclosure provides a memory test method. The method includes: determining a refresh cycle T, a designed attack resistance frequency F, and a single row read time t of a target repository; determining an attack row quantity N based on the refresh cycle T, the designed attack resistance frequency F, and the single row read time t; determining a group of target attack rows in the target repository based on a value of the attack row quantity N, where the group of target attack rows include N target attack rows, and at least two of the N target attack rows are spaced apart by one row; detecting, after reading the N target attack rows for X consecutive times, whether data exception occurs in all adjacent rows of the target attack rows, to complete one attack test.

Abstract: A temperature control apparatus is located at an interface between a coating and developing machine and a lithography machine, and includes a temperature detecting device and a temperature control device. The temperature detecting device is connected to the temperature control device. The temperature detecting device is configured to detect an actual temperature at the interface in real time. The temperature control device is configured to control the actual temperature at the interface to reach a target temperature when the actual temperature is not equal to the target temperature.