Abstract: An overlay pattern includes a light-transmitting region and a first light-proof region. The first light-proof region and the light-transmitting region are arranged on a same plane, and an area of the first light-proof region is larger than an area of the light-transmitting region. An orthographic projection of the first light-proof region on the plane and an orthographic projection of the light-transmitting region on the plane do not overlap and form a first rectangular region.

Abstract: A method of preparing an air gap includes: forming a first covering layer etching and removing part higher than a horizontal line where a top of the oxide layer is located; forming a first oxide layer on an etched plane; etching the first oxide layer; removing a part of the first oxide layer; reserving a rest part of the first oxide layer; taking a reserved first oxide layer as an oxide layer pattern; forming a second covering layer at a position of a removed part of the first oxide layer; removing the oxide layer pattern and the oxide layer.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate having a first surface and a second surface opposite to each other, and a transistor being arranged on the second surface; forming release holes in the substrate, the release holes extending into the transistors, bottoms of the release holes being located in channel regions of the transistors, and top surfaces of the release holes being flush with the first surface; and forming a conductive structure in the release holes.

Abstract: A data synthesizer includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to latch a first data under control of a first latch clock signal. The second input circuit is configured to latch a second data under control of the first latch clock signal. A phase of the first data is the same as a phase of the second data. The output circuit is connected to the first input circuit and the second input circuit. The output circuit is configured to output the first data and the second data in sequence.

Abstract: A method for forming the active area includes the following operations. A semiconductor substrate is provided. A first mask layer and a second mask layer are sequentially formed on a surface of the semiconductor substrate, in which the second mask layer has an initial pattern for forming the active area. A sacrificial layer covering the second mask layer is formed. The sacrificial layer and a portion of the second mask layer are removed to form a third mask layer with a preset thickness, in which the preset thickness is less than an initial thickness of the second mask layer. The active area is formed through the third mask layer and the first mask layer.

Abstract: Embodiments of the disclosure disclose a semiconductor device and a method manufacturing thereof. The semiconductor device includes a substrate as well as a first groove and a second groove located in the substrate, in which the second groove is formed by etching the substrate downwards from part of a bottom surface of the first groove, and a sidewall of the second groove retracts inward by a preset length relative to a sidewall of the first groove; a word layer including a first sub-portion located in the second groove and a second sub-portion located in the first groove, in which a gap is provided between a sidewall of the second sub-portion and that of the first groove; and a word line cover layer located in the first groove and covering the second sub-portion, in which an air gap structure at least located at the gap is provided in the word line cover layer.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, in which a gate structure is formed on the substrate; forming first side walls covering side surfaces of the gate structure, in which the first side walls have a first preset thickness in a direction parallel to a plane of the substrate; performing first ion implantation on the substrate on both sides of the gate structure exposed to the first side walls; removing a part of the first side walls to form second side walls, in which the second side walls have a second preset thickness in the direction parallel to the plane of the substrate; and performing second ion implantation on the substrate on both sides of the gate structure, in which doping types of the first ion implantation and the second ion implantation are different.

Abstract: An oscillating circuit comprises a constant voltage supply circuit, a constant current supply circuit and an oscillating circuit; the constant voltage supply circuit is configured to output constant voltage; the constant current supply circuit is configured to output constant current; and the oscillating circuit is connected to the constant voltage supply circuit and the constant current supply circuit, and is configured to generate an oscillating signal with a preset frequency according to the constant voltage and the constant current.

Abstract: A semiconductor memory training method includes: selecting two adjacent reference voltages from a plurality of reference voltages as a first reference voltage and a second reference voltage; obtaining a first minimum margin value for the plurality of target signal lines under the first reference voltage; obtaining a second minimum margin value for the plurality of target signal lines under the second reference voltage, according to a minimum margin value for each target signal line under the second reference voltage; determining a target interval for an expected margin value according to the first minimum margin value and the second minimum margin value, the expected margin value being the maximum one among the minimum margin values for the plurality of target signal lines under the plurality of reference voltages; and searching for the expected margin value in the target interval.

Abstract: The present disclosure relates to a method for generating a pattern of a memory, a computer-readable storage medium and a computer device, the method for generating a pattern of a memory includes: presetting mapping relationships between a physical address and a row, a column and a bank, and determining bits of the physical address corresponding to the row, the column and the bank; taking a preset number of values as setting data, the preset number being the same as a number of signal address lines in the memory; obtaining a command truth value table, which is used to define relationships between bits of the physical address and commands; determining values of the row, the column and the bank based on the command truth value table and the setting data; generating the pattern based on the values of the row, the column and the bank and the mapping relationships.

Abstract: Embodiments provide a method for data storage and comparison, a storage comparison circuit device, and a semiconductor memory. The storage comparison circuit device includes a latch and a comparator. The latch is configured to latch inputted first input data and output first output data and second output data. The first output data are the same as the first input data, whereas the second output data are different from the first input data, wherein the first output data and the second output data are respectively inputted into the comparator. The comparator is configured to receive second input data, the first output data and the second output data, and to output a comparison result. By using modular structures of the latch and the comparator, device data can be simplified for the latch and the comparator, chip area can be reduced, calculation amount can be reduced, and efficiency of data comparison can be improved.

Abstract: An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.

Abstract: A semiconductor structure includes: a substrate; a conductive via, a first conductive type transistor, and a second conductive type transistor located in substrate; a first metal layer located on substrate; and a second metal layer located on first metal layer. The first conductive type transistor is disposed on two sides of conductive via in first direction, and second conductive type transistor is disposed on two other sides of conductive via in a second direction perpendicular to first direction. The first metal layer includes at least one first metal line extending in first direction and electrically connected to a gate of first conductive type transistor. The second metal layer includes at least one second metal line extending in second direction and electrically connected to a gate of second conductive type transistor. The first metal line and second metal line intersect with each other to form a grid structure covering conductive via.

Abstract: A method for measuring an element concentration of a material includes: a material sample is irradiated with first electromagnetic waves; second electromagnetic waves radiated by the material sample are obtained under the action of the first electromagnetic waves; material property parameters of the material sample are determined by detecting the second electromagnetic waves; and an element concentration of the material sample is determined according to the material property parameters.

Abstract: A memory device and a forming method thereof are provided. The memory device includes: a semiconductor substrate, wherein multiple active regions are formed in the semiconductor substrate, and the multiple active regions are separated by multiple first trenches extending along a first direction and multiple second trenches extending along a second direction; a third trench, extending along the first direction and located in the semiconductor substrate at the bottom of the first trench; a bit line doped region, located in the semiconductor substrate on two sides of the third trench; a gate dielectric layer, located on a sidewall surface of the first trench and a sidewall surface of the second trench; a first dielectric layer that fills the third trench; a metal gate, located in the second trench and the first trench on the first dielectric layer.

Abstract: A mode register data processing module is configured to write, in response to a mode register write enable command, first preset data into a reserved mode register in a mode register; an external data transmission module is configured to write, in response to an enable signal, initial data into a memory array via an internal data transmission module according to the first preset data and a preset encoding rule, and is further configured to read target data from the memory array in response to a read command; and a comparison module is configured to determine whether there is an abnormal data transmission based on a comparison result of the first preset data and the target data, and store the comparison result to a preset position in the mode register.

Abstract: Embodiments relate to a transmission circuit, a transmission method, a storage apparatus, and a storage medium. The transmission circuit includes a comparison module and a data conversion module. The comparison module is configured to receive first data on a first data line and second data on a second data line, and compare the first data with the second data to output a comparison result indicating whether number of different bits between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width. The data conversion module is electrically connected to the first data line, the comparison module and the second data line, and is configured to invert the first data and transmit the inverted first data to the second data line when the comparison result is indicative of exceeding the preset threshold.

Abstract: A comparator includes a second-stage circuit, a first input circuit, a second input circuit, a first cross-coupled circuit and a second cross-coupled circuit. The first input circuit is configured to generate a first data terminal voltage and a first reference terminal voltage. The first cross-coupled circuit is configured to perform mutual positive feedback on the first data terminal voltage and the first reference terminal voltage to generate a first differential signal. The second input circuit is configured to generate a second data terminal voltage and a second reference terminal voltage. The second cross-coupled circuit is configured to perform mutual positive feedback on the second data terminal voltage and the second reference terminal voltage to generate a second differential signal. The second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a plurality of transistors arranged in a staggered manner, wherein the transistors share one source plate, a channel of the transistor is located on the source plate, and a channel length direction of the transistor is perpendicular to a surface of the source plate, and a material of the channel includes an oxide semiconductor; a plurality of drain contact members, electrically connected to drains of the transistors, wherein an odd number of transistors share one drain contact member, and the transistors sharing the same drain contact member are driven by a same word line; and a plurality of magnetic tunnel junctions, located on the drain contact members, wherein the magnetic tunnel junctions are electrically connected to the drain contact members in a one-to-one corresponding manner.

Abstract: A manufacturing method for capacitor structure includes: forming a dielectric layer on a first electrode, wherein the dielectric layer includes metal oxide layers doped with preset oxides, and part of the preset oxide and a metal oxide share oxygen atoms; and forming a second electrode on the dielectric layer, wherein the first electrode, the dielectric layer and the second electrode constitute a capacitor structure.