Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
  • Publication number: 20230176483
    Abstract: An exposure machine and an exposure method are provided in some embodiments of the present disclosure. The exposure machine includes: a detection module, configured to detect whether there are attachments on the surface of a reticle: a cleaning device, configured to clean the attachments on the surface of the reticle; and an exposure module, configured to expose the reticle having no attachments detected.
    Type: Application
    Filed: March 10, 2021
    Publication date: June 8, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Bin ZOU
  • Publication number: 20230178124
    Abstract: A memory chip stores a characterization parameter for characterizing a process corner of the memory chip, the memory chip further has a reference voltage with an adjustable value, the value of the reference voltage is adjustable based on the characterization parameter, and the memory chip adjusts, based on the reference voltage, a delay from reading out data from a memory cell to outputting the data through a data port.
    Type: Application
    Filed: April 30, 2022
    Publication date: June 8, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: SHU-LIANG NING
  • Publication number: 20230180457
    Abstract: A method for forming a capacitor includes: providing a substrate; sequentially forming a first sacrificial layer and a first support layer for covering the substrate; forming first openings penetrating through the first support layer; sequentially forming a second sacrificial layer and a second support layer for covering a remaining portion of the first support layer; forming through holes which sequentially penetrate through the second support layer, the second sacrificial layer, the remaining portion of the first support layer, and the first sacrificial layer; forming first electrode layers, each first electrode layer covering an inner wall of a respective one of the through holes; forming second openings penetrating through a remaining portion of the second support layer; and sequentially forming a dielectric layer and a second electrode layer for covering the first electrode layers, to form the capacitor.
    Type: Application
    Filed: February 1, 2023
    Publication date: June 8, 2023
    Applicants: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Mengmeng YANG, Xiaoling WANG
  • Publication number: 20230180464
    Abstract: A method includes the following operations for preparing a semiconductor structure, a semiconductor, and a semiconductor memory. A first dielectric layer and a first barrier layer are deposited on a substrate including an active area in sequence. A first mask including a first etching pattern is formed on the first barrier layer, and includes a groove extending in a first direction and uniformly distributed etching holes. Herein, the groove penetrates through the etching hole, and the depth of the etching hole is larger than that of the groove. Etching is performed along the first etching pattern, to remove the first barrier layer and etch the first dielectric layer to form a conductive channel.
    Type: Application
    Filed: June 20, 2022
    Publication date: June 8, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yexiao YU, Longyang CHEN, Zhongming LIU, Zhong KONG
  • Publication number: 20230176113
    Abstract: A chip testing method includes: a data receiving window corresponding to each chip to be tested is determined; a time adjustment parameter corresponding to each chip to be tested is determined according to the data receiving window corresponding to each chip to be tested and a data input window preset for a test machine is determined; an actual input time point corresponding to each chip to be tested is determined according to the time adjustment parameter corresponding to each chip to be tested; and data is inputted to each chip to be tested at the actual input time point corresponding to the each chip to be tested, to enable each chip to be tested to receive the data inputted by the test machine in the data receiving window corresponding to the each chip to be tested.
    Type: Application
    Filed: April 26, 2022
    Publication date: June 8, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Liang CHEN
  • Publication number: 20230176784
    Abstract: A memory system includes: a plurality of memory chips, wherein each of the memory chips has a parameter used to characterize a process corner of the memory chip; and a controller, wherein the controller is configured to: obtain the parameter of each of the memory chips, and adjust, based on the parameter, a delay of a read command sent to the memory chip corresponding to the parameter.
    Type: Application
    Filed: May 7, 2022
    Publication date: June 8, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: SHU-LIANG NING
  • Publication number: 20230176542
    Abstract: A method and device for monitoring production equipment and a storage medium includes: a measurement result of production equipment to be monitored is acquired; the measurement result of the production equipment to be monitored is evaluated on at least one evaluation dimension to obtain an evaluation result on each evaluation dimension; and a production state of the production equipment to be monitored is determined based on the evaluation result on the at least one evaluation dimension. The production state includes a normal state and an abnormal state. The at least one evaluation dimension includes at least one of a process level of products, a statistical significance of products or a distribution trend of products.
    Type: Application
    Filed: June 20, 2022
    Publication date: June 8, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shanshan HUA
  • Publication number: 20230178123
    Abstract: A memory chip is applied to the memory system, and the memory chip is configured to perform counting and obtain a count value after the memory chip is powered on and started, wherein the count value is used to represent a process corner of the memory chip, the memory chip further has a reference voltage with an adjustable value, the value of the reference voltage is adjustable based on the count value, and the memory chip adjusts, based on the reference voltage, a delay from reading out data from a memory cell to outputting the data through a data port.
    Type: Application
    Filed: May 6, 2022
    Publication date: June 8, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: SHU-LIANG NING
  • Patent number: 11670349
    Abstract: A memory circuit includes a precharge circuit and control circuit. The precharge circuit comprises a first precharge circuit, second precharge circuit, first power supply end, second power supply end, first control end, second control end and data end. The first precharge circuit is connected with the first power supply end, first control end and data end. The second precharge circuit is connected with the second power supply end, second control end and data end. A first precharge voltage is input into the first power supply end, and a second precharge voltage is input into the second power supply end. The control circuit is configured to control connection and disconnection between the data end and second power supply end and to control connection and disconnection between the data end and first power supply end.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: June 6, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Liang Zhang
  • Patent number: 11671106
    Abstract: A pulse signal generation circuit includes a clock frequency division component, a time delay component and a selection component. The clock frequency division component is configured to perform frequency division on a clock signal to generate a clock frequency division signal; the time delay component is configured to generate a time delay signal based on the clock frequency division signal; and the selection component is configured to receive the clock frequency division signal and the time delay signal at the same time, and select the clock frequency division signal and the time delay signal according to a preset condition to generate a pulse signal.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: June 6, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Enpeng Gao, Weibing Shang, Kangling Ji
  • Patent number: 11669015
    Abstract: A photolithography device includes: a fixed slot, configured to install and fix the light source; a sensing module, configured to sense the distance information between the light source and the fixed slot; a prompt module, configured to send prompt information according to the distance information; and a determination module, configured to determine the installation status of the light source according to the prompt information.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: June 6, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xueyu Liang
  • Publication number: 20230170885
    Abstract: A voltage conversion circuit and a memory are provided. The voltage conversion circuit includes a driving circuit and a receiving circuit. The driving circuit is powered by a first voltage, and outputs a first signal at an output end, a voltage of a high level of the first signal being less than the first voltage. The receiving circuit is powered by the first voltage, receives the first signal at a first input end, and receives a sampling signal at a second input end. The receiving circuit is configured to output a second signal according to the sampling signal, and a voltage of a high level of the second signal is equal to the first voltage.
    Type: Application
    Filed: January 20, 2023
    Publication date: June 1, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kangling JI
  • Patent number: 11662667
    Abstract: The present application provides an exposure machine, relates to semiconductor integrated circuit manufacturing technologies. The exposure machine includes a machine platform, a shielding device, and a drive device; the machine platform is provided with a recess portion, the recess portion has a top opening, a base and a placement table are disposed in the recess portion, the placement table is configured to carry a mask carrier, and the mask carrier can be placed on the placement table through the top opening; and the machine platform is further provided with a drive device and a movable shielding device, when the shielding device is at an initial position, the shielding device covers the top opening, and when the mask carrier needs to be placed on the placement table through the top opening, the drive device opens the shielding device to expose the top opening.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: May 30, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Bo Liu
  • Patent number: 11656245
    Abstract: A method and device for measuring dimension of a semiconductor structure are provided. A probe of an Atomic Force Microscope (AFM) is controlled at first to move a first distance from a preset reference position to a top surface of a semiconductor structure to be measured in a direction perpendicular to the top surface of the semiconductor structure to be measured, then the probe is controlled to scan the surface of the semiconductor structure to be measured while keeping the first distance in a direction parallel to the top surface of the semiconductor structure to be measured, amplitudes of the probe at respective scanning points on the surface of the semiconductor structure to be measured are detected, and a Critical Dimension (CD) of the semiconductor structure to be measured is determined according to the amplitudes of the probe at respective scanning points on the surface of the semiconductor structure.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: May 23, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zheng Li
  • Patent number: 11657204
    Abstract: Embodiments of the present application relate to the technical field of semiconductor, and disclose a design method of a wafer layout and an exposure system of a lithography machine. The design method of a wafer layout includes: providing a yield distribution map of a wafer under an initial wafer layout; determining a yield edge position of the wafer according to the yield distribution map; and calculating a new wafer layout according to a die size and the yield edge position.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: May 23, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Wei Xu
  • Publication number: 20230154869
    Abstract: A semiconductor structure includes a base layer, a device layer, and a stress propagating layer. The device layer is located on the base layer. The device layer includes a first dielectric layer and device structures. The first dielectric layer fills the device layer and isolates the device structures. The stress propagating layer is located on the device layer, includes a second dielectric layer and a plurality of stress propagating patterns arranged at intervals. The second dielectric layer fills the stress propagating layer and isolates the stress propagating patterns.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Sungjin KIM
  • Publication number: 20230143108
    Abstract: A furnace includes: a reaction chamber; a wafer boat assembly comprising multiple wafer boats each for bearing a substrate and an input pipeline assembly configured to introduce a gas are arranged in the reaction chamber; the introduced gas at least includes: silicon-containing reaction gas, nitrogen-containing reaction gas, impurity removal reaction gas, and cleaning gas; the input pipeline assembly includes a first gas input pipeline and a second gas input pipeline; the first gas input pipeline is provided with gas injection holes; the second gas input pipeline is formed by an elbow joint and two single pipes; the second gas input pipeline is provided with gas injection holes.
    Type: Application
    Filed: July 1, 2022
    Publication date: May 11, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: CHING-LUNG WANG
  • Publication number: 20230147501
    Abstract: A method for cleaning a substrate includes the following: exposing the substrate to a cleaning agent to remove impurities on a surface of the substrate; exposing the substrate to a dewetting chemical agent in a liquid phase to remove the cleaning agent on the surface of the substrate; solidifying the dewetting chemical agent in the liquid phase remaining on the surface of the substrate to obtain the dewetting chemical agent in a solid phase; and sublimating and removing the dewetting chemical agent in the solid phase.
    Type: Application
    Filed: August 30, 2022
    Publication date: May 11, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shih-Hung LEE
  • Patent number: 11646727
    Abstract: The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: May 9, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yinchuan Gu
  • Patent number: 11645151
    Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase and perform a first error checking and correction processing, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data; perform a second ECC encoding processing on the first data on which the first error checking and correction processing has been performed, to generate a second encoded data; and choose to transmit a to-be-written data to a memory die based on a selection signal in the writing phase, where the to-be-written data is either an initial data or a second data; and choose to transmit the initial data or third data in a reading phase based on a selection signal.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: May 9, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning