Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
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Patent number: 11646096Abstract: A method for accessing a memory includes the following. Location information of fail bits of multiple banks is acquired, backup circuits are distributed to the target banks from the multiple banks according to the location information of the fail bits by using a repair algorithm, a predicted repair result of the target bank is acquired, the availability of the target bank is detected according to the predicted repair result of the target bank, information indicating whether bits of target partial address bits of the target banks are predicted to be valid or invalid is acquired, and then predicted partial address bits are determined from the multiple address bits according to the information of the target partial address bits of the target banks to access a memory in a partial access mode according to the predicted partial address bits.Type: GrantFiled: April 18, 2022Date of Patent: May 9, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Xiangqian Jiang
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Patent number: 11645202Abstract: A parsing method includes the following: during parsing target bank, performing a row hammer operation on a logical row in target bank to determine a physical position relationship of the logical row; repeatedly performing the operation of performing the row hammer operation on the logical row in target bank to determine the physical position relationship of the logical row until all logical rows have been parsed; and determining a mapping relationship used for recording physical position relationships of multiple logical rows according to a linked list; where performing the row hammer operation on the logical row in target bank includes: acquiring a to-be-parsed logical row in target bank including multiple logical rows; performing the row hammer operation on the to-be-parsed logical row until at least one flipped logical row is obtained; and writing the at least one flipped logical row into the linked list.Type: GrantFiled: September 16, 2022Date of Patent: May 9, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Xiaolei Li, Baolei Han
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Publication number: 20230136990Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase and perform a first error checking and correction processing, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data; perform a second ECC encoding processing on the first data on which the first error checking and correction processing has been performed, to generate a second encoded data; and choose to transmit a to-be-written data to a memory die based on a selection signal in the writing phase, where the to-be-written data is either an initial data or a second data; and choose to transmit the initial data or third data in a reading phase based on a selection signal.Type: ApplicationFiled: May 2, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: SHU-LIANG NING
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Publication number: 20230137700Abstract: A base die is configured to receive first data and first encoded data in a writing phase, perform first error checking and correction processing, wherein the first encoded data is obtained by performing a first error correction code encoding processing on the first data, and transmit second data to a memory die in the writing phase, wherein the second data includes a first data after the first error checking and correction processing; the base die is further configured to receive the second data from the memory die in a reading phase, perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the reading phase, wherein the third data includes the second encoded data and the first data after the first error checking and correction processing.Type: ApplicationFiled: May 4, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: SHU-LIANG NING
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Publication number: 20230134961Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data and the first encoded data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data in the reading phase.Type: ApplicationFiled: May 1, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: SHU-LIANG NING
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Publication number: 20230136141Abstract: A method a for controlling a distribution sequence for a semiconductor device includes: acquiring the quantity of all chambers and an actual working duration of each radio frequency device in the machines; providing an optimal working duration of the radio frequency device to calculate an average interval; sorting all the data to form a first queue data set, and obtaining a difference between adjacent data in the first queue data set; using a difference between adjacent consecutive data as a feature value corresponding to the former or latter data in the consecutive data, and using data that does not correspond to the difference as a feature value corresponding to the data; obtaining a second queue data set and a third queue data set; and obtaining a distribution sequence of distributing N batches of wafers to all the radio frequency devices.Type: ApplicationFiled: April 11, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Chunyang WANG, Zhenxing LI, Yuming WANG, Fang WANG, SAN-CHEN CHEN, CHEN-HUA SHEN
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Publication number: 20230135418Abstract: A fuse structure includes a gate structure, a first electrode, a second electrode and an isolation structure. The gate structure is at least partially formed on an active area of a substrate. The first electrode is formed on the active area of the substrate and spaced apart from the gate structure. The second electrode is formed at least on a side of the gate structure. The isolation structure is formed between the active area and the second electrode.Type: ApplicationFiled: June 9, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: CHIH-CHENG LIU
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Publication number: 20230136979Abstract: An electrostatic protection circuit for a chip including a power supply pad and a ground pad, the electrostatic protection circuit includes: a monitoring assembly, configured to generate a trigger signal when an electrostatic pulse is present on the power supply pad; a discharge transistor connected between the power pad and the ground pad and configured to be turned on under control of the trigger signal to discharge electrostatic charges to the ground pad; and a control circuit connected to the monitoring assembly and configured to control a duration of the trigger signal generated by the monitoring assembly.Type: ApplicationFiled: July 2, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Ling ZHU, Kai TIAN
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Publication number: 20230133766Abstract: A method for detecting a layout of an integrated circuit includes: a finger structure is determined in the layout, the finger structure including at least one upper connection source-drain terminal and at least one upper connected via, the at least one upper connected source-drain terminal being electrically connected to an upper metal line through the at least one upper connected via; a number of the at least one upper connected source-drain terminal and a number of the at least one upper connected via are calculated; and for the finger structure, in response to the number of the at least one upper connected source-drain terminal being greater than the number of the at least one upper connected via, it is determined that the finger structure is an unqualified finger structure.Type: ApplicationFiled: June 8, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Miaomiao Chen
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Publication number: 20230139658Abstract: A base die is configured to: receive first data in a writing phase, perform error correction code encoding processing to generate encoded data, and transmit second data to a memory die in the writing phase, wherein the second data includes the first data and the encoded data; and receive the second data from the memory die in a reading phase, perform error checking and correction processing, and transmit third data in the reading phase, wherein the third data is the first data after the error checking and correction processing.Type: ApplicationFiled: May 4, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: SHU-LIANG NING
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Publication number: 20230134661Abstract: A board adapter device includes: a first adapter structure provided with a gold finger matched with a board of a target memory module, a second adapter structure provided with a connector matched with the gold finger, and a signal transmission structure including a first and second transmission module. The first transmission module is for connecting a data signal line, a clock signal line, an address signal line, and a control signal line of the gold finger to corresponding connecting lines of the connector. The second transmission module is configured to, when receiving a power input signal, convert the power input signal into a power output signal matched with a power supply of the target memory module, and transmit the power output signal to a power signal line of the connector.Type: ApplicationFiled: June 14, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Maosong MA, Jin QIAN, Jianbin LIU
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Publication number: 20230135245Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing on the first data and the second encoded data, and transmit a third data in the reading phase.Type: ApplicationFiled: May 1, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: SHU-LIANG NING
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Publication number: 20230136772Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on a first sub-data to generate a second encoded data, and transmit a second data to a memory die in the writing phase; where the second data includes the first sub-data, a second sub-data, the first encoded data, and the second encoded data; the base die is further configured to: receive the second data from the memory die in a reading phase, perform first error checking and correction processing on the first sub-data and the second encoded data, and transmit a third data in the reading phase.Type: ApplicationFiled: May 1, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: SHU-LIANG NING
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Publication number: 20230139664Abstract: A memory read-write circuit includes a sense amplifier and a control signal generation module. A power voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal, and a first power voltage controlled and supplied by the first control signal is greater than a second power voltage controlled and supplied by the second control signal. A control signal generation module is configured to control, in a normal read-write mode, a pulse duration for generating the first control signal to be a first duration, and control, in a refresh mode, the pulse duration for generating the first control signal to be a second duration, the second duration being less than the first duration.Type: ApplicationFiled: April 25, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yinchuan GU
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Publication number: 20230140073Abstract: The present application relates to a buried gate and a manufacturing method thereof. The method for manufacturing a buried gate includes: providing a substrate; forming a word line trench in the substrate; treating a surface of the word line trench to form concave structures on the surface of the word line trench; and, forming a conductive layer in the word line trench, convex structures matched with the concave structures being provided on a surface of the conductive layer.Type: ApplicationFiled: May 25, 2021Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: CHEONG SOO KIM, YONG GUN KIM, Xianrui HU, GuangSu SHAO
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Publication number: 20230133297Abstract: A method for manufacturing a semiconductor structure comprises: forming a stacked structure on a base having an array area and a peripheral area; forming a first mask layer on the stacked structure, in which the first mask layer corresponding to the array area has a first pattern; ion doping the first mask layer on the array area to obtain a doped first mask layer; and etching the stacked structure through the doped first mask layer to transfer the first pattern to the stacked structure.Type: ApplicationFiled: May 26, 2022Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: JUN XIA, SHIJIE BAI
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Publication number: 20230137705Abstract: The present disclosure provides a mask pattern for a semiconductor photolithography process and a semiconductor photolithography process. The mask pattern comprises: a pattern, the pattern comprising a light-transmitting area and a light-shielding area which are alternately arranged, the pattern having a boundary formed by an end portion of the light-transmitting area and an end portion of the light-shielding area, and an edge light-transmitting area being formed at the boundary. By the mask pattern of the present disclosure, a pattern with smooth edges can be formed on a wafer, and the edge roughness of the pattern is low, which meets the design requirements, thereby improving product quality and yield.Type: ApplicationFiled: November 20, 2020Publication date: May 4, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Congcong FAN
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Publication number: 20230126464Abstract: A semiconductor device includes: a substrate, and a plurality of conductors. A plurality of conductors are configured to form first electrodes of capacitor structures, and are distributed on one side of the substrate in rows and columns. Each of the conductors comprises a columnar body and a plurality of annular bumps. A part of an axial direction of the columnar body is intersected with the substrate. The annular bumps are arranged around the circumference of the columnar body, and a protruding direction of the annular bumps is parallel to the substrate. The plurality of annular bumps are distributed at intervals in the axial direction of the columnar body. Annular bumps of the conductors adjacent in row and column directions are staggered in a direction perpendicular to the substrate.Type: ApplicationFiled: May 24, 2021Publication date: April 27, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: PING-HENG WU
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Publication number: 20230126794Abstract: A semiconductor structure includes a substrate, comprising a first doped region; a first dielectric layer, located on the substrate; multiple deep trench capacitors, extending from the first dielectric layer to an inside of the substrate, in which each of the deep trench capacitors penetrates through the first doped region and comprises a serrated inner wall; multiple second doped regions, located in the substrate, in which each of the second doped regions surrounds a bottom of each deep trench capacitor and extends into the first doped region along an outer wall of the deep trench capacitor; and a first metal layer, located on the first dielectric layer and connected with the multiple deep trench capacitors.Type: ApplicationFiled: June 20, 2022Publication date: April 27, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: CHIH-CHENG LIU
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Patent number: 11637189Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a base and a plurality of stack structures that are located on the base, arranged at intervals, and extend along a first direction, wherein the stack structures each include a plurality of semiconductor layers arranged at intervals in a direction perpendicular to a surface of the base, and a top surface and a bottom surface opposite to each other of each of the semiconductor layers are each provided with a first sacrificial layer, a surface of the first sacrificial layer that is away from the semiconductor layer is provided with a second sacrificial layer, a same etching process has different etching rates for the first sacrificial layer and the second sacrificial layer, an isolation layer is provided between adjacent ones of the stack structures.Type: GrantFiled: September 15, 2022Date of Patent: April 25, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Guangsu Shao, Deyuan Xiao