Abstract: A new process for creating a transistor in an integrated circuit provides for two suicide formations, each independent of the other, from two metal depositions and formations steps. The process produces a sufficiently low resistance silicide layer over the source/drain region surfaces of the transistor while also creating a lower resistance silicide over the gate interconnects. In an example embodiment of the invention a near-planar isolation process is used applied such that the gate interconnect surfaces are co-planar. A first silicide layer is formed over the source/drain regions. A dielectric gap-fill material is applied. A planarization method such as chemical mechanical polishing is used to remove the gap fill material down to the top surface of the gate interconnect. A relatively thick suicide is then formed over the top surface of the gate interconnect.

Abstract: An optical tape drive including redundant optical heads to continue reading and writing data to an optical tape in the event of failure of one or more optical heads. The optical tape drive includes a plurality of optical heads, each capable of reading data from and writing data to an optical tape, detection logic that detects failure of any of the optical heads and control apparatus. The control apparatus positions each of the optical heads along the width of the optical tape, controls each of the optical heads to either read or write data, receives and moves the optical tape, detects failure of any of the optical heads and performs failure recovery by continuing to read and write data with remaining optical heads. The data throughput rate during failure recovery may be the same as the normal rate for some operations, such as direct read after write. Several different optical head configurations are contemplated.

Abstract: An external peripheral device connects through a flexible cable to an electrical connector which connects to a computer system. The flexible cable wraps around a cable wrap member that protrudes out of the peripheral device's housing, and the electrical connector snaps into a connector holder built into the peripheral device's housing. The cable wrap member and the connector holder permit the secure storage of the flexible cable and electrical connector during non-use or transportation of the device.

Abstract: A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, or as an interface bridge between a Fibre Channel Arbitrated Loop ("FC-AL") interface and the host and memory buses. The function of the multiple use chipset is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an FC-AL bridge interface is to be implemented. Selection of the type of bus bridge (AGP or FC-AL bridge interface) in the multiple use core logic chipset may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a FC-AL bridge interface device connected to the common AGP/ FC-AL bus. FC-AL information may be stored in the computer system main memory using the high speed FC-AL bridge interface.

Abstract: The present invention is a scalar quantity implemented as a process-pair resource manager. The process-pair implementation includes a concurrent aspect and a serial aspect. The concurrent aspect provides an object-like interface to the scalar quantity. Threads and processes access the scalar quantity by passing messages to the concurrent aspect. The concurrent aspect adds a description of each message as well as the result of processing each message to a transaction record. At the conclusion of a transaction, the concurrent aspect passes the transaction record to the serial aspect. The serial aspect then replays the transaction, using the transaction record. If the replay of the transaction is consistent with the transaction as recorded in the transaction record, the serial aspect sends a message to the concurrent aspect voting to commit the transaction. In turn, the concurrent aspect sends a message to the transaction manager forwarding the commit message.

Abstract: A computer system that includes a chassis and a removable module configured to be housed inside the chassis. The chassis includes an interface plate incorporated therewith. The interface plate is perforated to allow air to flow through the interface plate and along peripheral cards attached to the interface plate. The air that flows along the peripheral cards then flows through perforations in a cover that is used to secure the peripheral cards into their associated card slots. The cover then directs the air into a primary air passage used to exhaust air pulled through the chassis.

Abstract: A system for performing on-line reconfiguration of a disk array in which a source logical volume is reconfigured to a destination logical volume. Disk array configuration is invoked if a new physical drive is inserted, or a drive is removed. Reconfiguration can also be performed if the user desires to change the configuration of a particular logical volume, such as its stripe size. The disk array reconfiguration is run as a background task by firmware on a disk controller board. The reconfigure task first moves data from the source logical volume to a posting memory such as RAM memory. The reconfigure task operates one stripe at a time, with the stripe size being that of the destination logical volume. Once a stripe of data is moved into the posting memory, it is written back to corresponding locations in the destination logical volume. The reconfigure task continues until all data in the source logical volume have been moved into the destination logical volume.

Abstract: An improved system for scanning images is provided. The system includes a housing having a transparent support surface on which the document or other image being scanned is placed. The housing further contains an array of generally triangular-shaped prisms optically aligned. The array of prisms is coated with one of two types of electro-optical materials, one that makes the prisms reflective in the presence of an electromagnetic field and transparent in the absence of an electromagnetic field, and another that makes the prisms reflective in the absence of an electromagnetic field and transparent in the presence of an electromagnetic field. The electromagnetic field is created by applying a voltage across the coated prisms. A sequencer is used to activate individual electro-optical prisms so that the slices of the image can be reflected. By sequentially activating the electro-optical prisms, successive slices of the image can be presented to an image receptor disposed outside of the housing.

Abstract: A thermal management controller to regulate the operating temperature of high speed, high circuit density semiconductor dice in an electronic product. The thermal management controller monitors the temperature of a heat sink in thermal contact with the high speed, high circuit density semiconductor dice and also monitors the operational status of one or more specified devices which may increase the heat load within the electronic product. As the temperature of the heat sink increases and/or as specified devices increase the heat load in the electronic product, the thermal management controller will start cooling fans and/or increases the speed of the cooling fans to increase heat removal from the electronic product by forced convection.

Abstract: A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a commit-signal that is generated by control logic of the multiprocessor system in response to a memory reference operation issued by another processor sharing that cache. The commit-signal facilitates serialization among the processors and shared memory entities of the multiprocessor system by indicating the apparent completion of the memory reference operation to those entities of the system.

Abstract: A computer which includes modular structures incorporated therein provides enhanced serviceability. In a preferred embodiment, the computer has a chassis, a lid, a front bezel, an option card module, a system board module, a drive module, and a power supply module. The lid secures the option card module within the chassis. The option card module is removable from the chassis without disconnecting fasteners, option boards, or external cables therefrom. The system board module is received in the chassis and is secured therein by the option card module. The drive module has features which enable storage media devices to be conveniently installed therein and removed therefrom.

Abstract: A computer system with a SCSI backplane board has duplex-ready logic for switching the computer system between a SCSI simplex mode and a SCSI duplex mode. The duplex-ready logic includes a set of bus quick switches, a duplex-ready logic controller, and a set or sets of active terminators. The SCSI simplex mode and SCSI duplex mode are configured by the duplex-ready logic controller based on the number of SCSI cables present. If only a primary SCSI cable is present, the duplex-ready logic controller enables a SCSI simplex mode. To enable a SCSI simplex mode, the bus switches are enabled and the terminators are selectively enabled and/or disabled. If a primary SCSI cable and a secondary SCSI cable are present, the duplex-ready logic controller enables a SCSI duplex mode. To enable a SCSI duplex mode, the bus switches are disabled and the terminators are selectively disabled and/or enabled.

Abstract: A touch sensitive pad is formed of a touchpad surface overlaid with a matrix of two overlaid arrays of conductors spaced from each other by an intermediate dielectric. The conductors and dielectric are deposited as successive layers in the surface, which is formed of a suitable substrate material. The conductors in each of the arrays are in the form of spaced rows extending in alignment, and the two conductor arrays are arranged so that their respective sets of rows intersect, forming an X-Y matrix over the face of the touchpad. The two arrays are provided with different voltage levels so that a potential difference exists between them. A user touching an area or portion of the touchpad, whether with a finger, stylus, or pointer, shorts contacted ones of the X-Y matrix of conductors together in the area touched, giving rise to an electric current flow. The precise location of the contact area can be determined by processing firmware or software.

Abstract: The gangSIMM Memory Tester is a PWA which plugs directly into a CPU's SIMM slot. The gangSIMM Memory Tester contains a known good SIMM, which is connected directly to the CPU's bus. All memory functions for this SIMM slot is provided by the gold SIMM per normal SIMM operation. The CPU bus routed to the gold SIMM on the gangSIMM Memory Tester is also routed to a test bus via a buffer which provides increased drive capacity. The test bus is distributed in parallel to N number of SIMM slots located on the gangSIMM Memory Tester throughout a second set of tri-stating buffers. During read accesses to memory involving the CPUs SIMM slot location where the gangSIMM PWA is directly plugged into, data provided by the gold SIMM is compared on an individual basis with the data provided by an under-test SIMM. This operation occurs in-parallel for all under-test SIMMs.

Abstract: A computer system includes a data storage device on the first data bus, a device on the second data bus, and a bridge device capable of storing multiple data transactions for delivery from the second data bus to the first data bus. The bridge device includes a first data storage buffer preassigned to one of the transactions held in the bridge, and a buffer management element that assigns, if necessary, a second data storage buffer to the data transaction when the data associated with the transaction overflows the first data storage buffer.

Abstract: Apparatus, and an associated method, for determining the level of power supply redundancy in a modular computer system. Determination of the level of power supply redundancy is made dynamically, during on-line operation of the computer system. Reconfiguration of the computer system, such as to increase the load which must be powered by modular power supply components, or removal or addition of power supply components to form portions of the computer system cause initiation of a new determination of the level of power supply redundancy. Indications of inadequate levels of power supply redundancy are provided to a user of the computer system so that corrective action can be taken.

Abstract: Access to bus devices on a bus is granted in a computer system, with each bus device asserting a request signal to request the bus. A detector determines if a bus device is multi-threaded or single-threaded. An arbiter masks or does not mask the request signal of a retried bus device based on whether the bus device is a multi-threaded device. The arbiter masks the request signal of a retried bus device if it is a single-threaded device, but does not mask the request signal if the retried bus device is a multi-threaded device. The bus device request includes a delayed request transaction, and the bus includes a PCI bus.

Abstract: A convergence device system comprising a display monitor subsystem, a computer subsystem coupled to the display monitor subsystem, and a convergence functionality module adapted to provide a video signal to the computer subsystem. The display monitor subsystem is selectably operable in one of a first functional mode and a second functional mode, responsive to a control signal generated by the computer subsystem, wherein each of the modes corresponds to a set of selected display settings for the display monitor subsystem.