Abstract: A combination support and heat sink structure is mounted within a computer housing for pivotal movement between connected and disconnected positions and includes a pair of cooling plates, one air cooled and the other liquid cooled, carried in a spaced apart, parallel opposing relationship. The two cooling plates are movable toward and away from one another and a pair of manually operable spring clip members permit a processor card to be removably sandwiched and clamped between the cooling plates without the use of tools.

Abstract: A method for providing dual booting capabilities to a computer system is disclosed. The invention facilitates the installation of a plurality of operating systems on a computer system in any order such that the computer system is able to boot from any of the installed operating systems. The invention is particularly well suited for providing dual booting capabilities in both a DOS-based operating system and Windows NT when the DOS-based operating system is installed on the computer system subsequent to installation of Windows NT.

Abstract: A method for permitting access to secured computer resources based upon a two-piece user verification process. In the disclosed embodiment, the user verification process is carried out during a secure power-up procedure. At some point during the secure power-up procedure, the computer user is required to provide an external token or smart card to the computer system. The token or smart card is used to store an authentication value(s) required to enable secured resources. The computer user is then required to enter a plain text user password. Separate passwords can be used to enable various portions of the computer system. Once entered, a one-way hash function is performed on the user password. The resulting hash value is compared to an authentication value (token value) downloaded from the token. If the two values match, the power-on sequence is completed and access to the computer system and/or secured computer resources is permitted.

Abstract: The stretching of bitmap images in a computer system is accomplished by stretching each row of a source bitmap and storing the pixel information associated with the stretched row in a buffer, typically in main memory. The pixel information is transferred multiple times to the memory location associated with the destination bitmap, these memory locations generally reside in either main memory or in the frame buffer. Each time the buffer is written to the destination bitmap, an error term is adjusted by a predetermined amount. When the value of the error term meets a predefined criteria, the next row of the source bitmap is stretched and stored in the buffer and the process is repeated.

Abstract: A portable computer is provided with comparable performance to a desktop computer when docked at a docking station. When the portable computer is docked or physically coupled to the docking station, the microprocessor of the portable computer switches to an increased operating frequency. The onboard power supply of the portable computer is also disabled on docking, and the portable computer receives power from the docking station. Increased heat transfer capability is also enabled in the portable computer when it is docked, providing increased cooling to the portable computer. The portable computer thus overcomes the normal performance disparity between a portable computer system and a desktop computer system when the portable computer is docked.

Abstract: A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.

Abstract: An apparatus and a method resolve conflicts arising from the addition of a new or unconfigured device to a computer system having one or more system resources. The computer system has one or more existing devices, wherein each of existing devices has an existing configuration. Additionally, each of existing or new/unconfigured devices has one or more acceptable configurations. The apparatus resolves conflict by attempting to fit the new/unconfigured device into the system resources and if a non-conflicting configuration is available from the acceptable configurations for the new/unconfigured device, setting the configuration of the new/unconfigured device to the non-conflicting configuration. However, in the event that a non-conflicting configuration cannot be located, the apparatus requests one of the existing devices to select another configuration from its acceptable configurations until a non-conflicting configuration is available for the first device.

Abstract: An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.

Abstract: An image is stored as data representing the values of non-transparent pixels, and stored instructions corresponding to some pixels, resulting in a data structure. The image may be displayed by executing two types of instructions. A first type of instruction includes a command to skip pixels in a destination image. A second type of instruction comprises a command to copy pixels from the source data to the destination image.

Abstract: A computer system using posted memory write buffers in a bridge can implement the system management mode without faulty operation. The system management interrupt acknowledge signal is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory write buffer in the bridge execute prior to the appearance of the posted system management interrupt acknowledge signal. In this way, devices on a downstream bus will not be confused by the occurrence of posted memory write transactions into mistaking such transactions for system management mode operations. In this way, both bridges having posted write buffers and the system management mode may be utilized in efficient joint operation.

Abstract: An apparatus and method are disclosed for testing memory and display adapter components of a multi-tasking computer system. The apparatus obtains a memory block and sends a request to a memory virtual device driver (VxD) to reserve, commit and lock the memory block to a physical memory. In requesting the memory block, the apparatus computes the number of virtual memory pages spanned by the request, reserves the pages of virtual memory, commits the virtual memory to a physical memory, and locks the virtual memory to the physical memory. The apparatus then obtains a physical address for the physical memory and returns the physical address for testing. Next, the apparatus tests the memory block using a number of memory test procedures. After the testing completes, the apparatus decommits and unlocks the physical memory before it traverses to the next entry of the chain. This process is repeated until all entries in the virtual memory chain have been tested.

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

Abstract: A system and method of configuring VLANs of a multiple port bridging device by merging potentially conflicting VLANs. One or more VLANs are first defined by the user, and equivalent and subset VLANs are merged. The spanning tree procedure is then performed to determine a root identifier and a root port for each VLAN. The root identifier of each VLAN is compared with the other VLANs, and if equal, the root ports of the two VLANs are compared. If the root identifiers are the same and if the root ports are different for any two VLANs, the two VLANs are merged into a new VLAN. To merge two VLANs, all of the ports of both VLANs are combined to define a new VLAN. Preferably, each VLAN is compared with every other VLAN in this manner. The spanning tree procedure is then executed for the new VLAN, which is then compared to the other VLANs in the same manner.

Abstract: A computer having a heat sink structure incorporated therein provides efficient heat dissipation for heat generating components within the computer. In a preferred embodiment, a computer has a chassis, a circuit board with a heat generating device mounted thereon, and a structural member with a heat pipe disposed thereon. The heat pipe transfers heat from the heat generating device to a heat dissipating portion of the structural member. The structural member strengthens the chassis and provides convective transfer of the heat to the environment.

Abstract: A computer system has a mass storage device storing a file enabler associated with a file system for enabling file operations, a firmware memory storing a firmware routine, and a second memory. The computer system also has a microprocessor connected to load the file enabler stored on the mass storage device into the second memory and allow the firmware routine to access the file enabler stored in the second memory in file operations. The computer system may be a portable computer, and the firmware routine may be a hibernation routine.

Abstract: A distributed direct memory access (DMA) architecture where greater than seven DMA channels are provided and utilized. Alternative methods are disclosed for paging or swapping DMA channels so that more than seven may exist in a computer system, but only seven may be available at a time to remain compatible with conventional DMA controller software. In one method, channels may be assigned identical addresses, with one enabled at one time. In another method, channels are assigned unique addresses but the DMA master addresses only a subset of the total number of channels so that up to seven are available to compatible software at any one time.

Abstract: A portable computer docking system wherein the angle of the slot which receives the portable computer can be adjusted for ergonomic optimization, while keeping the docking unit as a whole stationary in its mounted location.