Abstract: An apparatus and a method for massaging audio signal perform interpolation, dynamic filtering, and panning on the audio signal represented as a matrix of input values. In the interpolation process, the input values are loaded into first and second vector registers, while fractional coefficients are loaded into a third vector register. Next, the first vector register is subtracted from the second vector register. Additionally, in a single operation, the routine performs a vector multiply operation between the second and third registers and accumulates the result of the vector multiply operation in the second register. The results are saved and the process is repeated until all input values in the matrix have been processed.

Abstract: A multiport polling system for a network switch including a plurality of network ports, each including receive and transmit buffers. Each port includes port status logic for providing status signals indicative of whether a corresponding port has received data from a network device and whether a corresponding port has available space to receive data to transmit to a network device. The network switch further includes a switch manager for controlling data flow between the ports. The switch manager includes polling logic for periodically polling the port status logic of each port for receiving the status signals, and a memory for storing values indicative of the status signals for each port. In this manner, all of the ports are simultaneously polled in a singe query and the receive and transmit status of each port is maintained in the memory.

Abstract: A technique for reducing skew between clock signals in a digital system requiring multiple clock signals. The system preferably is implemented on a printed circuit board. An oscillator circuit provides a periodic signal to a clock buffer which generates multiple periodic clock signals. The clock signals are provided to various destination points on the printed circuit board. The rising and falling edges of each clock signal generated by the clock buffer do not occur precisely at the same time as the rising and falling edges of the other clock signals. This misalignment of clock edges, or skew, is detrimental to system performance, but is reduced substantially by connecting all of the clock buffer's output clock signals together at a single physical point or node. Accordingly, the printed circuit board traces carrying each of the clock signals are routed to a single point node. A single point node is used to reduce skew caused by the clock buffer.

Abstract: A computer system including a host bus, a processor that asserts addresses between a lowest address and a highest address, at least one peripheral component interconnect (PCI) bus coupled to the host bus, at least one PCI device coupled to the PCI buses, and system memory devices that are mapped between the lowest address and an upper system memory address defined by PCI memory. Each PCI device has memory that is mapped in reverse and descending order in the PCI memory, which is located between a predetermined upper PCI memory address and the upper system memory address below the upper PCI memory address. The determination of the upper system memory through the reverse and descending mapping enables increased usage of system memory. The PCI devices coupled through each host PCI bus and its corresponding subordinate PCI buses are mapped together, resulting in a segment in the PCI memory for each host PCI bus.

Abstract: A keyboard matrix of a keyboard has drive lines including a set of lines to be selectively activated for detection of depressed keys and scan lines including a set of lines to be selectively monitored for detection of depressed keys. The keyboard matrix includes circuitry for connecting one of the drive lines with one of the scan lines for providing an identification of the keyboard.

Abstract: A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

Abstract: A current-mode control system for a switching power supply which provides logarithmic compensation to a peak primary current of a variable frequency, fully discontinuous switching power supply. A ramp voltage generator generates a ramp voltage that is furnished to a control circuit. The control circuit compares the voltage level of the ramp signal to the voltage level of a control voltage. The control voltage is provided by an error amplifier and is a function of an output voltage of the converter. The control circuit allows a primary switching current to exist in the converter until the ramp voltage renders the control voltage. The ramp voltage logarithmically compensates the peak of the primary current by adjusting the ramp voltage. This logarithmic compensation provides a relatively constant output power over a large input voltage range.

Abstract: A routable operand and selectable operation processor multimedia extension unit is employed to stretch pixel bit images in a video system using an efficient, parallel technique. For a series of pixels in a row, a series of interpolation values are established, based on multiples of a reciprocal of a stretch factor. For each interpolation value, the integral portion is used to establish the appropriate two source pixels, and the fractional portion then provides weighting of those pixel values. The various source pixels and interpolation values are routed using the operand routing and operated upon using the vector selectable operations, yielding two destination pixels calculated in parallel.

Abstract: An automated system for facilitating creation of a compatible rack-mountable component personal computer.

Abstract: A computer system that automatically and securely executes registered programs immediately prior to a transition to a reduced energy consumption state. A registrar table specifying registered programs and a secure modification detection value for each registered program are maintained in system management mode memory or other secure memory space in the computer system. A system management interrupt is generated following a request to remove power from the computer system or the occurrence of an event that triggers an energy saving mode. The system management interrupt handler routine then generates a current modification detection value for each registered program. The current modification detection values are compared with the secure modification detection values. Execution of a registered program is permitted if the values match. After all registered programs have been executed, the computer system automatically powers down or enters an energy saving mode.

Abstract: A method and apparatus provide communication in a telephone system connected to an external phone line, wherein the telephone system has a telephone line, a telephone, a phone interface unit coupled to the telephone and the telephone line, a computer system, and a computer interface unit coupled to the computer system and the telephone line. A bias voltage on the telephone line is detected to determine if the telephone is on-hook or off-hook, a ringing voltage on the telephone line is detected to determine if an external call is incoming, and a first carrier transmitted by the phone interface unit is detected. A second carrier is transmitted using the computer interface unit under control of the computer system. Detection of the bias voltage, ringing voltage, and/or first carrier is communicated to the computer system. An off-hook condition is indicated if the line bias voltage is less than an off-hook bias threshold voltage.

Abstract: A computer system which provides for slowing the effective speed of a microprocessor. The microprocessor includes a disabling input that when deactivated disables operations of the microprocessor on the processor bus. A computer system according to the invention periodically deasserts this signal with the certain duty cycle, allowing the microprocessor to continue to perform necessary functions at an effective rate compatible with older microprocessors, but never requiring an actual clock frequency change. This periodic deassertion is performed in response to a memory refresh counter that periodically counts down to zero and is reloaded. By comparing an input/output register with the refresh counter, and by adjusting the input/output register, the deasserting signal to the processor is periodically deasserted with a selectable duty cycle.

Abstract: A portable docking and precharging station with an AC adapter with automatically optimized output voltage and power. An IIC communications link between the computer and AC adapter carries signals which adjust the AC adapter's voltage and power settings, depending on the charge state of the battery and whether the computer is on or off. If the computer is on, full output power is provided from the AC adapter. If the computer is off, the output power from the AC adapter is reduced so that the current cannot exceed the battery manufacturer's recommended charging rates. Preferably the regulated output voltage and the current limit are both changed when the change between modes occurs.

Abstract: The present invention relates to a secondary channel for a point-to-point burst style bus associated with a computer system. The point-to-point bus may originate as a standardized bus from a fibre channel controller. The point-to-point bus connects to another circuit which may be a bridge circuit, a minicomputer or a peripheral device. A secondary channel is also connected to the point-to-point bus and is adapted to share the bus by receiving information having predetermined addresses. The information recieved by the secondary channel can be stored in a memory that is shared with a processor. Command/control information can be extracted from the point-to-point bus before data is transferred through the bridge circuit in order to allow the data to be acted on more quickly by processing/storage devices since the control data was already made available to the storage devices via the secondary channel.

Abstract: A multiple-way cache memory system incorporating circuitry for selectively enabling the sense amplifiers in a given memory bank only when the memory bank contains data that is being accessed. In the disclosed embodiment of the invention, each bank of memory incorporates a bank of at least one sense amplifier that is enabled by a separate sense amplifier control signal. The sense amplifiers in each memory bank are controlled independent of the address decoding logic. Instead, the sense amplifier control signal for each memory bank is generated from tag RAM read hit information and read address data. Preferably, no more than one bank of sense amplifiers is enabled at a time, Power consumption in the cache memory system is thereby greatly reduced.

Abstract: A portable computer docking station has a molded plastic housing within the interior of which are a ported speaker structure operative at low, mid and high frequencies, and a nonported speaker structure operative only at mid-to-high frequencies. The ported speaker structure has a ported enclosure section formed integrally with an exterior wall portion of the housing and having an open side. A first speaker is mounted on a lid member at an opening therein, with the lid member being secured to the ported enclosure section over the open side thereof with a seal member being sandwiched between the lid member and the enclosure section, and a sound absorbing structure being disposed within the enclosure section under the first speaker. The nonported speaker structure includes a second speaker supported on a second wall portion of the housing.

Abstract: A method for entering and manipulating spreadsheet cell data is described. The present invention provides a method for determining the target cell for written information and for scaling the information to fit within the boundaries of the target cell. A multi-tiered character recognition scheme is used to improve the accuracy and speed of character recognition and translation of handwritten data. The original handwritten data is preserved so that either the translated data or original data may be displayed. The present invention also provides for improved editing of cell entries by allowing a plurality of editing tools to be selected. Manipulation of blocks of data can be accomplished with simple gestures. Arithmetic, statistical and logical functions can be invoked with a single command.

Abstract: A computer includes a flexible member or tube fabricated from thermally conductive carbon fibers for transferring heat from a first portion, such as a base section of a portable computer, to a second portion, such as the display section of a portable computer, where the sections of the computer move between an open operating position and a closed position. The flexible member, fabricated from conductive fibers, is positioned so as to experience torsion upon opening the portable computer. A first heat pipe is thermally connected with a microprocessor in the base section at one end and at the other end is coaxially attached within the member or tube. A second heat pipe is similarly coaxially attached to the other end of the member or tube.

Abstract: An isolation transformer comprises two core pieces mounted to cooperate to provide flux paths, one of the core pieces being shaped so that a central flux path is defined by a central leg of the core, at least two magnetically coupled windings surrounding the central flux path, and an isolation layer sandwiched between the windings.