Abstract: An auxiliary power transistor which is switched in common with the primary power transistor, and which isolates the voltage-monitoring circuit when the primary power transistor is off. Thus the signal for sensing the secondary current is connected only when the power transistor is turned on, and high voltages in the sensing logic are avoided. This is particularly advantageous for systems where the turn-off times of the power transistor are sought to be synchronized with current zero-crossings. This current-zero-crossing technique may be used to detect zero-crossings of current on a secondary-side switch.

Abstract: A method of detecting and correcting errors in a memory subsystem of a computer is described. The method includes beginning a write operation of N data bits to a memory, generating M check bits from the N data bits, writing the N data bits and the M check bits to the memory, reading the N data bits and M check bits from the memory, generating X syndrome bits from the N data bits and the M check bits, and using the X syndrome bits to detect and correct errors. Preferably, the M check bits are generated also from A address bits corresponding to the location in memory to which the N data bits and M check bits are to be written.

Abstract: A system and method to reduce power consumption in a portable computer system while allowing the CDROM drive to continue playing audio CDs. When the system enters a suspend mode, the status of the CDROM drive is checked, and if it is playing an audio CD, it remains powered, otherwise power to the CDROM drive is also suspended. The system recognizes when the audio CD is finished playing and then places the CDROM drive into the suspend mode.

Abstract: A PCI repeater coupled between a primary bus and a secondary bus includes logic to allow downstream and upstream bursting across the repeater. The PCI repeater is operable to echo transactions in either an upstream or downstream direction. During configuration, the PCI repeater snoops configuration cycles on the primary bus to build an address map of devices on the primary bus. The PCI repeater then uses the address map as a lookup table as a positive determination of whether to forward a transaction upstream.

Abstract: A configuration manager for configuring a network device remotely coupled thereto and an associated computer-implemented method for configuring the network device. The configuration manager includes a configuration script stored in a memory subsystem of a computer system and first and second software modules respectively executable by a processor subsystem of the computer system. The configuration script contains a series of executable instructions for constructing a configuration file and a bootptab file for a first specified type of network device. By executing the instructions contained in the configuration script, the first software module may construct a configuration file suitable for upload to a network device and a bootptab file suitable for identifying the network device.

Abstract: A base cabinet system is provided for a laptop computer, on which the laptop can be placed for expanded home-based use. A reinforced removable cover arches over the top of the base cabinet so that the laptop can be slid into position on top of the base cabinet and beneath the cover, and the monitor rested on the top of the cover; when one wishes to use the laptop display, the monitor and cover are easily removed to permit tilt-up of the laptop display. Special retaining means are provided to assure that the cover seats itself and remains in its proper installed position, and special guides are provided to assure that when the laptop is slid into position the connector on its rear side will mate properly with the corresponding connector on the base cabinet.

Abstract: A distributed direct memory access (DMA) architecture where DMA controllers are modified to create isolated DMA channels. Each isolated channel includes its own set of uniquely addressable registers which provide functional compatibility with conventional DMA controllers. A DMA master interacts compatibly with the computer system and transparently communicates special cycles to the isolated DMA channels to cause the distributed DMA architecture to appear as the DMA controllers. The DMA master spawns special cycles to the isolated channels for sharing common write data with multiple channels and merging read data into a single DMA controller compatible register. Channel 4 cascading is also handled via tracking registers and special cycles to maintain disable and masking functionality of channel 4 as it effects channels 0-3.

Abstract: A computer system or computer server system having redundant devices that are periodically checked in order to determine whether the redundant devices would be operational if the primary devices failed. The primary and redundant devices are in electrical communication with a controller circuit which, in turn, is responsive to a microprocessor and/or the computer's operating system. The primary and redundant devices can be hot-pluggable so that the computer system does not need to be powered down when and if the primary or redundant devices need to be replaced.

Abstract: In a microcomputer system implementing cache memory, a multiple-way cache is implemented in a single-bank memory. Instead of using chip output enables on a separate physical chip for each way of the multiple-way cache, an address line of a single bank of memory is used to select between ways. In this way, fewer parts can be used, and a single-bank memory can be used for a multiple-way cache.

Abstract: A portable computer is housed in an integral multi-purpose carrying case. The case protects the portable computer against damage when closed, yet the case is easily opened for use of the computer while in the case. Ergonomic wrist and arm support are provided to a user of the computer when by the case when it is opened. The case also furnishes dissipation of heat from the computer during use while it is resting on a user's lap.

Abstract: A method for displaying information about computer files to a user on a display in an environment simulating three dimensional space includes displaying a category of files as a container having a size related to its distance from a predefined portion of the display.

Abstract: A computer application stored on a storage medium (e.g., a portable storage medium such as a compact disk) is automatically launched. Initialization information expressed in accordance with a predefined syntax is stored on the storage medium. Also stored in the computer is "launching" information sufficient, together with the initialization information, to enable the computer to launch the application. The application is automatically launched, without user intervention, by reading the initialization information and using it in connection with the launching information stored in the computer.

Abstract: An electrodeless lamp apparatus of high efficiency employs a reflection system that allows the lamp to reabsorb light energy. The energy is redirected back to the light to provide increased system efficiency. The redirected light is of the wrong polarization and/or wrong parts of the color spectrum. The lamp efficiency is increased because of the optical pumping as well as the reuse (after some downshifting) of the returned light. In one embodiment, a projection system provides an image source or projection engine that includes the improved high efficiency lamp of the present invention.

Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g.

Abstract: A computer system including a serial bus host controller and host controller driver. The host controller driver providing data structures for the host controller to operate on. The data structures having a linking mechanism for processing lists of descriptors, and alternate buffer configurations for receiving data from the serial bus devices.

Abstract: A computer system is powered by a battery pack, the battery pack including either nickel-based batteries or lithium-ion based batteries. Either of the two battery packs can be interchanged without modification to the system.

Abstract: A computer system using posted memory write buffers in a bridge can implement the stop clock acknowledge special cycle without faulty operation. The stop clock acknowledge transaction is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory write buffer in the bridge execute prior to the appearance of the posted stop clock acknowledge transaction. In this way, bridges having both posted write buffers and the stop clock special cycle may be utilized in efficient joint operation.

Abstract: A high-speed, hardware based translation system for translating frames from one frame format to another frame format is disclosed. According to one embodiment, the frame translation system for translating a frame associated with a computer network from a first format to a second format includes a storage buffer for temporarily storing the frame of the first format; and a format translator for retrieving portions of the frame in the first format from said storage buffer, identifying the second format from at least one of the retrieved portions of the frame in the first format, and outputting portions of the frame in the second format. The frame translation system may also include a counter for counting a length of the frame in the first format. The translation system according to the invention can translate frames of incoming data to another format at a rate of greater than 150k frames/seconds.