Abstract: A processor having the prior three user addressing modes and a new virtual system mode (VSM). The user modes include real mode, protected mode and virtual 8086 mode. In VSM, the processor can utilize the VSM addressing mechanism and the mode of operation prior to entering VSM. Transitions from the user modes to virtual system mode can be made by indirect calls through a call gate or through vectored entries. While in VSM the processor can utilize VSM memory and I/O space modes, but can also directly utilize the I/O space and memory of the user mode present prior to entry into VSM by using a segment override. The upper 16 MB of the virtual system mode memory space (0xff000000 through 0xffffffff) is designated as non-mapped virtual system mode memory. Virtual system mode logical addresses below 0xff000000 will be translated to physical addresses by the current page table if paging is enabled (protected mode).

Abstract: A computer system which utilizes processor boards including a first level cache system integrated with the microprocessor, a second level external cache system and a third level external cache system. The second level cache system is a conventional, high speed, SRAM-based, writeback cache system. The third level cache system is a large, writethrough cache system developed using conventional DRAMs as used in the main memory subsystem of the computer system. The three cache systems are arranged between the CPU and the host bus in a serial fashion. Because of the large size of the third level cache, a high hit rate is developed so that operations are not executed on the host bus but are completed locally on the processor board, reducing the use of the host bus by an individual processor board. This allows additional processor boards to be installed in the computer system without saturating the host bus. The third level cache system is organized as a writethrough cache.

Abstract: A computer system according to the invention includes a posted write cache for writing to a mass storage subsystem. Upon restart, the computer system determines whether the mass storage subsystem has been interveningly written to by another computer system since the computer system last wrote to that mass storage subsystem. If so, the computer system flushes its posted write cache, thus prevent invalid data from being written to the mass storage subsystem.

Abstract: Method for predicting an imminent failure of a disk drive. A plurality of attributes are selected for monitoring during operation of the disk drive. These attributes may include self-preserving attributes, performance attributes, error rate attributes, and even count attributes. An initial value is determined for each one of the selected attributes. A threshold value is then selected for each of the attributes. The disk drive is then monitored for occurrences of the self-preserving, performance, error rate and event count attributes. Each time an occurrence of the attributes is monitored, the initial value for that attribute is updated and normalized. The updated normalized value for the attribute is then compared with the corresponding threshold for that attribute and an imminent failure of the disk drive is predicted if the normalized updated value of the attribute exceeds the threshold therefor.

Abstract: A tower type CPU unit portion of a computer system has a housing with a top side wall in which a spaced series of parallel, elongated support wells are formed. The wells are sized and configured to removably receive relatively small lower edge portions of portable media storage devices, such as compact discs in their protective cases, and support the devices in generally upright positions atop the CPU unit. When the CPU unit is positioned on the floor to one side of the desk upon which the balance of the computer system is placed, the compact discs are conveniently stored in an easily seen, readily accessible and otherwise unused location without requiring a space-consuming storage area on the desktop work area.

Abstract: A system for allowing a peripheral device to be inserted directly into a port of a computer system while the computer system is powered on. The insertion of a peripheral device into the computer system port is automatically detected, and a configuration operation is automatically performed when insertion of the peripheral device is detected. The system also allows a plurality of peripheral devices to be connected to a single port of a computer system by automatically determining the number of peripheral devices and assigning a unique address to each of the peripheral devices. The peripheral device may have a host port for communicating with the computer system, a slave port for connecting to a slave device, and a device manager which identifies if a slave device is connection.

Abstract: A portable computer docking station in which the computer is inserted vertically into a vertical slot. An additional slot receives modular accessories (such as a CD drive, floppy disk drive, or extra battery) to be inserted. Connectors in the vertical slot provide power to the computer, and provide connection to external display and user input devices, and also provide electrical connection from the computer to whichever module is in the additional slot, and also provides charging if the additional module is a battery.

Abstract: The elongated body portion of a lap-supportable remote infrared computer keyboard is contoured on its bottom side, by means of a spaced pair of arcuately shaped, generally parallel recesses that extend between front and rear sides of the body, to conform to upper side portions of a seated user's thighs. Positioned in the recesses are spaced series of elongated outwardly projecting parallel ribs which longitudinally extend transversely to the lengths of the recesses and serve to frictionally inhibit front-to-rear shifting of the lap-supported keyboard along the user's thighs. The key member portions of the keyboard are positioned on the top side of the body between left and right end portions thereof. On the top side of one of these end portions is a pointing device, representatively a track ball, and on the top side of the other end portion are a pair of selection buttons.

Abstract: In a microcomputer system using a multiple-way cache memory subsystem, the way of the next microprocessor operation is predicted, and either the output enables of the cache are predriven, or, in a single-bank multiple-way cache, the address bit which acts as a way selection is appropriately set. The way prediction used is based not on the address being accessed in the cache, but instead on the last processor code read, or the last processor code or data read. This permits the cache memory subsystem to respond more quickly on hits to the appropriate way, and also allows for slower cache memories to be used without reducing performance.

Abstract: A cursor control system for a computer includes a small video camera mounted above the keyboard portion of the computer and pivotable to selectively view (1) a central observation zone generally over the keyboard, (2) a horizontally offset observation zone to the left of the keyboard, or (3) a horizontally offset observation zone to the right of the keyboard. The image received by the video camera of a computer user's hand placed within the selected observation zone is transmitted to cursor control circuitry which monitors the presence, configuration and movement of the hand. When the hand is placed in a first predetermined configuration and moved into and through the zone, the circuitry switches the computer from a keyboard typing mode to a cursor positioning mode, tracks the hand movement through the zone, and correspondingly moves the cursor on the computer display screen.

Abstract: A congestion management scheme for managing traffic in a data communication system having a plurality of port blocks at least one of which may be connected to a communication medium, the congestion management scheme including a structure for determining whether a sender is congested, a structure for determining whether a receiver is congested, and a structure for determining whether a RX FIFO is congested and a structure for determining a memory buffer, associated with at least one of the sender and the receiver, is congested. The congestion scheme further includes a structure for handling traffic by taking one of the preferred actions depending upon the congestion indicators.

Abstract: Data is transmitted between a first device and a second device connected by the communications channel in a computer system. The first device generates a first clock and the second device generates a second clock. The first clock is provided to the second device and the second clock is provided to the first device. Data received by the first device over the communications channel from the second device is synchronized to the first clock. The receiving logic in the first device includes a first-in-first-out buffer The received data is stored in a first-in-first-out buffer until the data is synchronized to the first clock. The first and second clocks have the same frequency.

Abstract: An add-in circuit card is secured in an electronic device. A clamp is movably coupled to the electronic device and is configured to releasably engage the card upon movement of the clamp from a card engagement position to a card disengagement position. A switch may control electrical power to the card, the switch operated by the clamp such that movement of the clamp between the engagement and disengagement positions closes and opens the switch.

Abstract: A multi-boot apparatus allows a portable computer to boot from a predetermined list of bootable data storage devices, even if the data storage devices have been relocated during operation. The computer system has a hard disk bay and multi-bay for accepting one or more data storage devices and/or battery packs. During initialization, the invention retrieves a previously entered IPL sequence from a configuration setup table stored in the nonvolatile RAM of the portable computer. Next, the invention queries each bay and determines the device connected to each bay, including the data storage device and the battery pack, if one is present. The invention then determines if a remapping of the data storage drives is necessary to ensure that the device at the beginning of the IPL order is the first drive in the BIOS boot sequence. If so, the invention remaps the drives such that the device is at the first drive in the BIOS boot sequence.

Abstract: A universal battery pack which includes an integral power converter and a dynamically adjustable output voltage. The default output voltage is set by an optional resistor connection, which shifts the voltage-dividing ratio into the error amplifier. In a multiple-battery configuration, the output voltages of the separate battery modules are preferably set to slightly different values. Thus the battery module with the highest output voltage setting will be completely exhausted first. This results in automatic battery switchover, without requiring any control algorithm or logic for execution of the switchover.

Abstract: A new and improved apparatus and method for rebuilding a replacement disk of a fault tolerant, mass storage drive array subsystem of a computer system. The method calls for a microprocessor to check a stripe for consistency. If the stripe is inconsistent, the microprocessor rebuilds a predetermined number of stripes. If the checked stripe is consistent, then the microprocessor checks a next stripe and repeats the above-described process. Because the drive array subsystem receives both system requests and rebuild requests, the present invention allows a user to select the drive array subsystem's priority in processing system requests versus rebuild requests, thereby allowing greater system access to the drive array subsystem during peak times of system requests.

Abstract: A dynamic hibernation time apparatus monitors and ensures that battery packs in a computer system have sufficient energy capacity to sustain a proper saving of the hibernation file into the hard disk drive. The invention determines the memory size of the computer and adds the storage space needed to store the chip register contents to arrive at the determination of the hibernation file size. Next, the time necessary to save the hibernation file on the disk data storage device and the hibernation energy required to operate the disk data storage device to completely save the hibernation file are determined. When the battery capacity drops within a range of the previously computed hibernation energy, a warning message is generated at the user and the hibernation file is saved. The computer is shut down after the hibernation file has been properly saved.

Abstract: A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When a PCI device executes a memory read, the processor cache and L2 cache are snooped in parallel with the memory read operation. Data is not provided until the snoop operation is complete. If the snoop operation indicates a modified location, a writeback operation is performed before data is provided to the PCI bus. If data is coherent between the memory and caches, data is provided from the memory to the PCI bus.

Abstract: Performance of a bus in a computer system is monitored. A predetermined total period is counted, and usage of the bus for data transfers during the total period is measured. The bus is monitored for active cycles and a period is counted in which the active cycles are present during the total period. The bus is monitored for data transfer cycles and a period is counted in which the data transfer cycles are present during the total period. Bus efficiency is measured based on the active period and data transfer period. Read data usage on the bus is also measured. A first amount of data read by a first device is monitored, and a second amount of read data used by a second bus device is monitored. The read efficiency is determined based on the first and second amounts.